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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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2026-01-13[AMDGPU] Put back ProperlyAlighedRC helper functionsusers/cdevadas/putback-ProperlyAlighedRCChristudasan Devadasan1-0/+22
2026-01-13moved the implementation to SIInstrInfo.Christudasan Devadasan1-149/+1
2026-01-13[AMDGPU] Make getNumSubRegsForSpillOp externally available (NFC).Christudasan Devadasan1-3/+3
2026-01-13incorporated review comments.users/cdevadas/add-spill-offset-to-sgpr-spill-pseudosChristudasan Devadasan1-3/+3
2026-01-13[AMDGPU] Introduce Offset field in SGPR spill PseudosChristudasan Devadasan1-2/+3
2026-01-05[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#1...LU-JOHN1-1/+1
2025-12-09[AMDGPU] Scavenge a VGPR to eliminate a frame index (#166979)Anshil Gandhi1-3/+29
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault1-14/+0
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad1-2/+2
2025-11-14AMDGPU: Remove getProperlyAlignedRC (#167993)Matt Arsenault1-22/+0
2025-11-13AMDGPU: Really use AV classes by default for vector classes (#166483)Matt Arsenault1-0/+8
2025-11-13[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)Sergei Barannikov1-3/+5
2025-11-13AMDGPU: Start to use AV classes for unknown vector class (#166482)Matt Arsenault1-0/+11
2025-11-12[CodeGen] Use MCRegUnit in two more TRI methods (NFC) (#167680)Sergei Barannikov1-1/+1
2025-11-11AMDGPU: Remove wrapper around TRI::getRegClass (#159885)Matt Arsenault1-11/+0
2025-11-11AMDGPU: Start using RegClassByHwMode for wavesize operandsMatt Arsenault1-4/+1
2025-11-11AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)Matt Arsenault1-11/+4
2025-11-11AMDGPU: Replace some uses of getOpRegClass with getRegClass (#167447)Matt Arsenault1-1/+1
2025-10-29[AMDGPU] Support true16 spill restore with sram-ecc (#165320)Stanislav Mekhanoshin1-1/+24
2025-10-27[AMDGPU] Use implicit operand to preserve liveness of COPY (#164911)Jeffrey Byrnes1-1/+5
2025-10-12[llvm] Use [[fallthrough]] instead of LLVM_FALLTHROUGH (NFC) (#163086)Kazu Hirata1-2/+2
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault1-1/+2
2025-10-07AMDGPU: Stop using the wavemask register class for SCC cross class copies (#1...Matt Arsenault1-3/+1
2025-10-06AMDGPU: Stop handling AGPR case in getCrossCopyRegClass (#161800)Matt Arsenault1-3/+0
2025-10-03AMDGPU: Fix trying to constrain physical registers in spill handling (#161793)Matt Arsenault1-7/+3
2025-09-12CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)Matt Arsenault1-2/+2
2025-09-05AMDGPU: Use switch to implement getRegPressureSetLimit (#156993)Matt Arsenault1-4/+5
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin1-2/+55
2025-09-02AMDGPU: Add VS_64_Align2 class (#156132)Matt Arsenault1-0/+5
2025-08-05[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)Stanislav Mekhanoshin1-0/+2
2025-07-28AMDGPU: Move getMaxNumVectorRegs into GCNSubtarget (NFC) (#150889)Matt Arsenault1-60/+1
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus1-0/+2
2025-07-18[AMDGPU] Use SIRegisterInfo to compute used registers. NFCI (#149051)Diana Picus1-4/+4
2025-07-09[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)Brox Chen1-3/+1
2025-07-03AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)Changpeng Fang1-0/+1
2025-07-01AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive...Changpeng Fang1-0/+3
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus1-1/+5
2025-06-13Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#14...Diana Picus1-14/+0
2025-06-04[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)Kazu Hirata1-3/+3
2025-06-03[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#133242)Diana Picus1-0/+14
2025-05-05[AMDGPU] Remove implicit definition of register group when restoring the last...Ryan Buchner1-1/+3
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus1-7/+64
2025-04-23Revert "[AMDGPU] Support block load/store for CSR" (#136846)Diana Picus1-64/+7
2025-04-23[AMDGPU] Support block load/store for CSR (#130013)Diana Picus1-8/+65
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus1-0/+1
2025-03-17[AMDGPU] frame index elimination hit assertion for scavenged nonreg (#130287)Pankaj Dwivedi1-16/+21
2025-03-12[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)Brox Chen1-0/+67
2025-03-06AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)Matt Arsenault1-7/+1
2025-03-06AMDGPU: Add amdgpu-agpr-alloc attribute to control AGPR allocation (#128034)Matt Arsenault1-11/+45
2025-03-05AMDGPU: Handle s_add_u32 in eliminateFrameIndex (#129628)Matt Arsenault1-2/+3
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