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path: root/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
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2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad1-2/+2
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault1-1/+1
2025-11-07AMDGPU: Minor SDWA pass cleanups (#166629)Matt Arsenault1-10/+11
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault1-2/+3
2025-09-22[AMDGPU] Skip debug uses in SIPeepholeSDWA (#160092)Jay Foad1-1/+2
2025-09-03[AMDGPU] si-peephole-sdwa: reuse getOne{NonDBGUse,Def} (NFC) (#156455)Frederik Harwath1-26/+2
2025-06-26[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)Jun Wang1-0/+4
2025-05-26[AMDGPU] si-peephole-sdwa: Remove dead code from createSDWAversion (#141462)Frederik Harwath1-50/+7
2025-05-26[AMDGPU] si-peephole-sdwa: Disable V_CNDMASK_B32 conversion with sext (#140760)Frederik Harwath1-0/+15
2025-05-14[AMDGPU] si-peephole-sdwa: Fix cndmask vcc use for wave32 (#139541)Frederik Harwath1-0/+1
2025-05-05[AMDGPU] Fix a warningKazu Hirata1-0/+1
2025-05-05[AMDGPU] SIPeepholeSDWA: Handle V_CNDMASK_B32_e64 (#137930)Frederik Harwath1-9/+68
2025-03-03[AMDGPU] Account for existing SDWA selections (#123221)Frederik Harwath1-42/+154
2025-01-24[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)Frederik Harwath1-2/+5
2025-01-23Revert "[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#1239...Nico Weber1-5/+2
2025-01-23[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#123942)Frederik Harwath1-2/+5
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-2/+2
2024-09-11[AMDGPU][NewPM] Port SIPeepholeSDWA pass to NPM (#107049)Akshat Oke1-17/+39
2024-07-17[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)Jay Foad1-11/+8
2024-07-01[AMDGPU] Reset kill flags for multiple uses of SDWAInst OpsJeffrey Byrnes1-0/+7
2024-06-14[AMDGPU] Adding multiple use analysis to SIPeepholeSDWA (#94800)Brian Favela1-15/+53
2024-03-06[AMDGPU] Don't form sext/abs/neg fp8 cvt (#83843)Pierre van Houtryve1-0/+9
2024-02-28[AMDGPU] Fix SDWA 'preserve' transformation for instructions in different bas...Valery Pykhtin1-4/+3
2023-10-19[AMDGPU] PeepholeSDWA: Don't assume inst srcs are registers (#69576)Pierre van Houtryve1-4/+8
2023-06-11[NFC] Replace ;; with ;David Green1-1/+1
2023-02-07[CodeGen] Make more use of MachineOperand::getOperandNo. NFC.Jay Foad1-1/+1
2023-01-23[MC] Make more use of MCInstrDesc::operands. NFC.Jay Foad1-2/+2
2022-12-14[AMDGPU] Stop using make_pair and make_tuple. NFC.Jay Foad1-1/+1
2022-12-13[CodeGen] llvm::Optional => std::optionalFangrui Song1-2/+3
2022-12-02[Target] Use std::nullopt instead of None (NFC)Kazu Hirata1-7/+7
2022-11-25[AMDGPU] Use std::optional in SIPeepholeSDWA.cpp (NFC)Kazu Hirata1-1/+3
2022-11-17Handling ADD|SUB U64 decomposed Pseudos not getting lowered to SDWA formYashwant Singh1-17/+8
2022-11-08[AMDGPU] Add & use `hasNamedOperand`, NFCPierre van Houtryve1-17/+13
2022-02-18[AMDGPU][NFC] Fix typosSebastian Neubauer1-6/+6
2021-12-01[AMDGPU] Add a regclass flag for scalar registersChristudasan Devadasan1-1/+1
2021-11-26[AMDGPU] Make vector superclasses allocatableChristudasan Devadasan1-1/+1
2021-11-12[AMDGPU][NFC] Fix typosNeubauer, Sebastian1-1/+1
2021-01-20[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargetsdfukalov1-1/+2
2021-01-12[AMDGPU] Add _e64 suffix to VOP3 InstsJoe Nash1-3/+3
2021-01-07[NFC][AMDGPU] Reduce include files dependency.dfukalov1-27/+0
2020-08-20[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegisterJay Foad1-8/+4
2020-08-13[AMDGPU] Inhibit SDWA if target instruction has FIStanislav Mekhanoshin1-0/+10
2020-07-16AMDGPU: Rename add/sub with carry out instructionsMatt Arsenault1-10/+10
2020-05-27AMDGPU: Fix dropping MI flags when rewriting instructionsMatt Arsenault1-9/+16
2020-02-12Fix unused function warning (PR44808)Hans Wennborg1-5/+7
2019-12-02AMDGPU: Fixed indeterminate map iteration in SIPeepholeSDWATim Renouf1-2/+3
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-1/+1
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-7/+7
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-8/+8
2019-06-16[AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin1-2/+3
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