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path: root/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
AgeCommit message (Expand)AuthorFilesLines
2025-11-22[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)tyb08071-0/+5
2025-11-14[AMDGPU] Use std::variant in ArgDescriptor. (#167992)Craig Topper1-1/+3
2025-10-25[Target] Add "override" where appropriate (NFC) (#165083)Kazu Hirata1-1/+1
2025-10-10AMDGPU/GlobalISel: Fix using wrong regbank for smfmac (#162762)Matt Arsenault1-0/+6
2025-10-07AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)Matt Arsenault1-4/+6
2025-09-12[AMDGPU] Support lowering of cluster related instrinsics (#157978)Shilei Tian1-0/+5
2025-08-08[AMDGPU] AsmPrinter: Unify arg handling (#151672)Diana Picus1-0/+15
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus1-0/+6
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus1-0/+7
2025-06-13Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#14...Diana Picus1-15/+0
2025-06-03[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#133242)Diana Picus1-0/+15
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus1-0/+32
2025-04-23Revert "[AMDGPU] Support block load/store for CSR" (#136846)Diana Picus1-32/+0
2025-04-23[AMDGPU] Support block load/store for CSR (#130013)Diana Picus1-0/+32
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus1-0/+17
2025-02-23AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)Matt Arsenault1-5/+0
2024-12-18[AMDGPU] Make max dwords of memory cluster configurable (#119342)Ruiling, Song1-0/+9
2024-11-12[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)Christudasan Devadasan1-0/+4
2024-11-07Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)dyung1-7/+0
2024-11-07[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)Akshat Oke1-0/+7
2024-11-05[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)Akshat Oke1-0/+3
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-7/+10
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan1-3/+14
2024-09-13Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)Diana Picus1-0/+3
2024-09-12Revert "Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)...Diana Picus1-3/+0
2024-09-12Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)" (#108173)Diana Picus1-0/+3
2024-09-11[AMDGPU] Fix leak and self-assignment in copy assignment operator (#107847)Fraser Cormack1-8/+14
2024-09-10Revert "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)Vitaly Buka1-3/+0
2024-09-10[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic (#105822)Diana Picus1-0/+3
2024-06-25AMDGPU: Add plumbing for private segment size argument (#96445)Nicolai Hähnle1-0/+1
2024-06-02Use llvm::less_first (NFC) (#94136)Kazu Hirata1-4/+1
2024-05-03[AMDGPU] Convert PrologEpilogSGPRSpills from DenseMap to sorted vector (#90957)Jay Foad1-8/+24
2024-03-12[AMDGPU] Adding the amdgpu_num_work_groups function attribute (#79035)Jun Wang1-0/+10
2024-01-24[AMDGPU] Move architected SGPR implementation into isel (#79120)Jay Foad1-23/+9
2024-01-24[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)Christudasan Devadasan1-1/+8
2024-01-23[AMDGPU] Remove getWorkGroupIDSGPR, unused since aa6fb4c45e01Jay Foad1-16/+0
2023-12-17[AMDGPU] Track physical VGPRs used for SGPR spills (#75573)Carl Ritson1-0/+1
2023-09-25[AMDGPU] Add DAG ISel support for preloaded kernel argumentsAustin Kerbow1-0/+11
2023-09-12[AMDGPU] Add utilities to track number of user SGPRs. NFC.Austin Kerbow1-42/+8
2023-08-21[AMDGPU] Add IsChainFunction to the MachineFunctionInfoDiana Picus1-0/+2
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault1-18/+21
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka1-21/+18
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-18/+19
2023-07-07[AMDGPU] Enable whole wave register copyChristudasan Devadasan1-0/+2
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan1-1/+32
2023-06-29[AMDGPU] Reserve SGPR pair when long branches are presentBrendon Cahoon1-0/+12
2023-05-19[AMDGPU] Fix warningsKazu Hirata1-3/+6
2023-04-08AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnableMatt Arsenault1-0/+6
2023-03-14[Target] Use *{Set,Map}::contains (NFC)Kazu Hirata1-1/+1
2023-02-23[AMDGPU] Split SIModeRegisterDefaults out of AMDGPUBaseInfo. NFC.Jay Foad1-5/+4
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