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path: root/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus1-0/+7
2025-04-13[AMDGPU] Use llvm::find and llvm::find_if (NFC) (#135582)Kazu Hirata1-1/+1
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus1-1/+2
2025-03-14[AMDGPU] Avoid repeated hash lookups (NFC) (#131419)Kazu Hirata1-5/+7
2025-03-06AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)Matt Arsenault1-1/+4
2025-02-23AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)Matt Arsenault1-48/+6
2025-01-23[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)Lucas Ramirez1-3/+2
2025-01-17[AMDGPU] Fix printing hasInitWholeWave in mir (#123232)Stanislav Mekhanoshin1-1/+1
2025-01-10[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)Austin Kerbow1-0/+2
2024-12-18[AMDGPU] Make max dwords of memory cluster configurable (#119342)Ruiling, Song1-4/+8
2024-11-07Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)dyung1-5/+4
2024-11-07[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)Akshat Oke1-4/+5
2024-11-05[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)Akshat Oke1-0/+3
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-1/+1
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan1-6/+22
2024-09-26[AMDGPU] Merge the conditions used for deciding CS spills for amdgpu_cs_chain...Christudasan Devadasan1-2/+8
2024-09-19[LLVM] Use {} instead of std::nullopt to initialize empty ArrayRef (#109133)Jay Foad1-1/+1
2024-08-19[AMDGPU] Move AMDGPUCodeGenPassBuilder into AMDGPUTargetMachine(NFC) (#103720)Christudasan Devadasan1-1/+0
2024-07-17[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)Jay Foad1-1/+2
2024-07-17[AMDGPU] Use range-based for loops. NFC. (#99047)Jay Foad1-3/+3
2024-07-17[AMDGPU] clang-tidy: use emplace_back instead of push_back. NFC.Jay Foad1-4/+2
2024-07-16[AMDGPU] clang-tidy: replace macro with enum. NFC.Jay Foad1-1/+1
2024-06-25AMDGPU: Add plumbing for private segment size argument (#96445)Nicolai Hähnle1-0/+6
2024-06-25AMDGPU: Remove an outdated TODO (#96446)Nicolai Hähnle1-1/+0
2024-04-29[AMDGPU] Fix typo in #89773Jay Foad1-1/+1
2024-04-24[AMDGPU] Allow WorkgroupID intrinsics in amdgpu_gfx functions (#89773)Jay Foad1-1/+2
2024-03-21AMDGPU: Infer no-agpr usage in AMDGPUAttributor (#85948)Matt Arsenault1-29/+1
2024-03-12[AMDGPU] Adding the amdgpu_num_work_groups function attribute (#79035)Jun Wang1-0/+2
2024-02-09[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)Diana Picus1-8/+4
2024-01-24[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)Christudasan Devadasan1-11/+43
2023-12-17[AMDGPU] Track physical VGPRs used for SGPR spills (#75573)Carl Ritson1-1/+2
2023-12-13[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)Piotr Sobczak1-1/+1
2023-12-11[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)Kazu Hirata1-1/+1
2023-12-06[AMDGPU] Introduce isBottomOfStack helper. NFC (#74288)Diana Picus1-1/+1
2023-11-14[AMDGPU] Use immediates for stack accesses in chain funcs (#71913)Diana1-1/+1
2023-11-08[AMDGPU] Callee saves for amdgpu_cs_chain[_preserve] (#71526)Diana1-0/+8
2023-09-25[AMDGPU] Add DAG ISel support for preloaded kernel argumentsAustin Kerbow1-0/+28
2023-09-12[AMDGPU] Add utilities to track number of user SGPRs. NFC.Austin Kerbow1-60/+10
2023-08-21[AMDGPU] ISel for amdgpu_cs_chain[_preserve] functionsDiana Picus1-1/+14
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault1-35/+34
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka1-34/+35
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-35/+34
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan1-0/+16
2023-06-29[AMDGPU] Reserve SGPR pair when long branches are presentBrendon Cahoon1-0/+2
2023-04-08AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnableMatt Arsenault1-1/+6
2023-03-08[AMDGPU] Extend WorkGroupID* codegen for compute shadersChristudasan Devadasan1-1/+4
2022-12-21CodeGen: Don't lazily construct MachineFunctionInfoMatt Arsenault1-6/+11
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan1-18/+14
2022-12-17Fix unused variable warning in release build, NFC.Haojian Wu1-2/+2
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-14/+18
generated by cgit v1.1 at 2025-09-29 03:53:25 +0000