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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2026-01-13moved the implementation to SIInstrInfo.Christudasan Devadasan1-0/+146
2026-01-13[AMDGPU] Introduce Offset field in SGPR spill PseudosChristudasan Devadasan1-3/+4
2026-01-13[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subr...Christudasan Devadasan1-1/+1
2026-01-09[AMDGPU] Add liverange split instructions into BB Prolog (#117544)Christudasan Devadasan1-7/+27
2026-01-05[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#1...LU-JOHN1-4/+4
2025-12-29AMDGPU: Avoid crashing on statepoint-like pseudoinstructions (#170657)Matt Arsenault1-0/+8
2025-12-15[AMDGPU] Stop handling soft waitcnts in pseudoToMCOpcode. NFC. (#172278)Jay Foad1-1/+2
2025-12-12[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_IN...Juan Manuel Martinez Caamaño1-0/+24
2025-12-04[AMDGPU] Add verifier for flat_scr_base_hi read hazard (#170550)Stanislav Mekhanoshin1-0/+11
2025-12-03[AMDGPU] Take BUF instructions into account in mayAccessScratchThroughFlat (#...Pierre van Houtryve1-2/+3
2025-12-02[AMDGPU] Handle phys regs in flat_scratch_base_hi operand check (#170395)Stanislav Mekhanoshin1-1/+2
2025-12-02[AMDGPU] Prevent folding of flat_scr_base_hi into a 64-bit SALU (#170373)Stanislav Mekhanoshin1-0/+11
2025-11-28[AMDGPU][NPM] Fix CFG invalidation detection in insertSimulatedTrap (#169290)Prasoon Mishra1-0/+4
2025-11-25[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)Jay Foad1-1/+1
2025-11-24AMDGPU: Fix a comment (#169403)Nicolai Hähnle1-3/+4
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn1-2/+2
2025-11-20AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)Nicolai Hähnle1-2/+2
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN1-2/+2
2025-11-15[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)LU-JOHN1-0/+15
2025-11-14AMDGPU: Fix verifier error when waterfall call target is in AV register (#168...Matt Arsenault1-18/+26
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad1-15/+14
2025-11-13[AMDGPU] Lower S_ABSDIFF_I32 to VALU instructions (#167691)Mariusz Sikora1-0/+36
2025-11-12CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (#166213)Nicolai Hähnle1-4/+53
2025-11-11AMDGPU: Remove override of TargetInstrInfo::getRegClass (#159886)Matt Arsenault1-12/+0
2025-11-11AMDGPU: Remove wrapper around TRI::getRegClass (#159885)Matt Arsenault1-2/+3
2025-11-11[AMDGPU] Generate s_lshl?_add_u32 (#167032)LU-JOHN1-7/+29
2025-11-10CodeGen: Remove TRI arguments from stack load/store hooks (#158240)Matt Arsenault1-5/+3
2025-11-10CodeGen: Remove TRI argument from reMaterialize (#158229)Matt Arsenault1-3/+3
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault1-6/+5
2025-11-10CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)Matt Arsenault1-1/+2
2025-11-07[AMDGPU] Delete redundant s_or_b32 (#165261)LU-JOHN1-5/+33
2025-11-06Reland: CodeGen: Record MMOs in finalizeBundle (#166689)Nicolai Hähnle1-0/+3
2025-11-04[AMDGPU][NFC] Avoid copying MachineOperands (#166293)LU-JOHN1-4/+4
2025-11-02[llvm] Remove "const" in the presence of "constexpr" (NFC) (#166109)Kazu Hirata1-3/+3
2025-10-31[AMDGPU][NFC] Refactor SCC optimization (#165871)LU-JOHN1-43/+41
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN1-6/+63
2025-10-20AMDGPU: Refactor three-address conversion (NFC) (#162558)Nicolai Hähnle1-69/+71
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr1-63/+6
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN1-6/+63
2025-10-17[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)Brox Chen1-0/+61
2025-10-14[AMDGPU] Simplify vcc handling in copyPhysReg. NFC. (#163340)Jay Foad1-22/+10
2025-10-13[AMDGPU] Enable saving SHARED_BASE to VCC (#163244)carlobertolli1-1/+1
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault1-48/+17
2025-10-03[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass (#161764)Brox Chen1-0/+26
2025-10-03AMDGPU: Stop trying to constrain register class of post-RA-pseudos (#161792)Matt Arsenault1-2/+0
2025-10-03AMDGPU: Remove dead code trying to constrain a physical register (#161790)Matt Arsenault1-15/+8
2025-10-01[AMDGPU][InsertWaitCnts] Refactor some helper functions, NFC (#161160)Pierre van Houtryve1-0/+53
2025-09-24[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)Brox Chen1-0/+7
2025-09-23[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]Philip Reames1-2/+2
2025-09-22[AMDGPU] Skip debug uses in SIInstrInfo::foldImmediate (#160102)Jay Foad1-2/+2
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