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path: root/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-12-06[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#17...Philip Reames1-12/+6
2025-11-21[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)Christudasan Devadasan1-0/+11
2025-11-04[AMDGPU] Fix handling of FP in cs.chain functions (#161194)Robert Imschweiler1-1/+3
2025-10-20[AMDGPU] Fix iterator invalidation during frame lowering (#163952)Diana Picus1-5/+7
2025-10-03AMDGPU: Fix trying to constrain physical registers in spill handling (#161793)Matt Arsenault1-1/+2
2025-10-02[Codegen] Add a separate stack ID for scalable predicates (#142390)Benjamin Maxwell1-0/+1
2025-09-16[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)Carl Ritson1-12/+9
2025-09-04[AMDGPU] Tail call support for whole wave functions (#145860)Diana Picus1-3/+17
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin1-1/+3
2025-08-01[AMDGPU] Ensure non-reserved CSR spilled regs are live-in (#146427)macurtis-amd1-0/+7
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus1-10/+77
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus1-6/+7
2025-05-17[llvm] Use llvm::is_sorted (NFC) (#140399)Kazu Hirata1-5/+6
2025-04-27[AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)Brox Chen1-1/+1
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus1-0/+204
2025-04-23Revert "[AMDGPU] Support block load/store for CSR" (#136846)Diana Picus1-204/+0
2025-04-23[AMDGPU] Support block load/store for CSR (#130013)Diana Picus1-0/+204
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus1-9/+62
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve1-0/+1
2025-02-20[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#...Craig Topper1-2/+3
2025-01-24[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)Aaditya1-8/+12
2025-01-14[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)Guy David1-1/+1
2024-11-20[AMDGPU] Fix restores in chain functions (#116193)Diana Picus1-1/+2
2024-10-18[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::has...Alex Rønne Petersen1-1/+1
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-6/+6
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan1-32/+27
2024-09-26[AMDGPU] Merge the conditions used for deciding CS spills for amdgpu_cs_chain...Christudasan Devadasan1-14/+4
2024-09-24[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. ...Pravin Jagtap1-4/+9
2024-09-20[AMDGPU] Use Lo_32 and Hi_32 helpers (NFC) (#109413)Nikita Popov1-4/+4
2024-09-13Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)Diana Picus1-4/+8
2024-09-12Revert "Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)...Diana Picus1-8/+4
2024-09-12Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)" (#108173)Diana Picus1-4/+8
2024-09-10Revert "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)Vitaly Buka1-8/+4
2024-09-10[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic (#105822)Diana Picus1-4/+8
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-0/+6
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-6/+0
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-0/+6
2024-05-29[AMDGPU] Reserved private memory register during PEI (#93536)Pankaj Dwivedi1-0/+1
2024-05-01[AMDGPU] change order of fp and sp in kernel prologue (#90626)Gang Chen1-6/+6
2024-02-23[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)Ivan Kosarev1-8/+7
2024-02-09Revert "[AMDGPU] Compiler should synthesize private buffer resource descripto...Jan Patrick Lehr1-67/+41
2024-02-08[AMDGPU] Compiler should synthesize private buffer resource descriptor from f...alex-t1-41/+67
2024-02-05[AMDGPU] Insert spill codes for the SGPRs used for EXEC copy (#79428)Christudasan Devadasan1-5/+12
2024-01-24[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)Christudasan Devadasan1-1/+4
2024-01-18[AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186)Jay Foad1-1/+1
2023-12-15[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)Mirko Brkušanin1-2/+2
2023-11-14[AMDGPU] Use immediates for stack accesses in chain funcs (#71913)Diana1-8/+8
2023-11-08[AMDGPU] Fix -Wunused-variable in SIFrameLowering.cpp (NFC)Jie Fu1-3/+1
2023-11-08[RegScavenger] Simplify state tracking for backwards scavenging (#71202)Jay Foad1-1/+1
2023-11-08[AMDGPU][PEI] Set up SP for chain functionsDiana Picus1-2/+21
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