aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-11-18[NFC] Check operand type instead of opcode (#168641)Shilei Tian1-21/+13
2025-11-18[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its...Shilei Tian1-0/+41
2025-11-15[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)LU-JOHN1-22/+11
2025-11-14[TableGen] Split *GenRegisterInfo.inc. (#167700)Ivan Kosarev1-1/+1
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad1-2/+2
2025-11-11AMDGPU: Remove wrapper around TRI::getRegClass (#159885)Matt Arsenault1-3/+4
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault1-2/+2
2025-11-07[AMDGPU][MachineVerifier] test failures in SIFoldOperands (#166600)Abhay Kanhere1-0/+4
2025-11-05AMDGPU: Delete redundant recursive copy handling code (#157032)Matt Arsenault1-29/+0
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault1-5/+4
2025-10-03[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass (#161764)Brox Chen1-1/+3
2025-10-03AMDGPU: Fix constrain register logic for physregs (#161794)Matt Arsenault1-1/+2
2025-09-27AMDGPU: Check if immediate is legal for av_mov_b32_imm_pseudo (#160819)Matt Arsenault1-0/+9
2025-09-26[AMDGPU] Avoid constraining RC based on folded into operand (NFC) (#160743)Josh Hutton1-4/+9
2025-09-17[AMDGPU] Fold copies of constant physical registers into their uses (#154410)Stanislav Mekhanoshin1-4/+11
2025-09-16CodeGen: Surface shouldRewriteCopySrc utility function (#158524)Matt Arsenault1-15/+2
2025-09-12CodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault1-3/+2
2025-09-03AMDGPU: Fold 64-bit immediate into copy to AV class (#155615)Matt Arsenault1-6/+19
2025-09-03AMDGPU: Avoid using exact class check in reg_sequence AGPR fold (#156135)Matt Arsenault1-2/+4
2025-09-02AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)Matt Arsenault1-24/+35
2025-08-27AMDGPU: Remove special case of SGPR_LO class in imm folding (#155518)Matt Arsenault1-8/+0
2025-08-27AMDGPU: Fold mov imm to copy to av_32 class (#155428)Matt Arsenault1-12/+2
2025-08-26AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks (#154501)Matt Arsenault1-34/+51
2025-08-18Revert "[AMDGPU] Fold copies of constant physical registers into their uses (...Stanislav Mekhanoshin1-7/+2
2025-08-18[AMDGPU] Fold copies of constant physical registers into their uses (#154183)Stanislav Mekhanoshin1-2/+7
2025-08-07[AMDGPU] bf16 clamp folding (#152573)Stanislav Mekhanoshin1-3/+7
2025-08-04[AMDGPU] Fold into uses of splat REG_SEQUENCEs through COPYs. (#145691)Ivan Kosarev1-1/+8
2025-07-30[AMDGPU] Add v_cvt_sr|pk_bf8|fp8_f16 gfx1250 instructions (#151415)Stanislav Mekhanoshin1-0/+1
2025-07-26AMDGPU: Fix not folding splat immediate into VGPR MFMA src2 (#150628)Matt Arsenault1-0/+4
2025-07-21[AMDGPU] Prevent folding of FI with scale_offset on gfx1250 (#149894)Stanislav Mekhanoshin1-4/+10
2025-07-16AMDGPU: Fix assert when multi operands to update after folding imm (#148205)macurtis-amd1-4/+10
2025-06-26AMDGPU: Handle folding vector splats of inline split f64 inline immediates (#...Matt Arsenault1-33/+70
2025-06-26AMDGPU: Fix tracking subreg defs when folding through reg_sequence (#140608)Matt Arsenault1-179/+251
2025-06-10AMDGPU: Try constant fold after folding immediate (#141862)Matt Arsenault1-0/+6
2025-05-30[AMDGPU] Fix SIFoldOperandsImpl::canUseImmWithOpSel() for VOP3 packed [B]F16 ...Daniil Fukalov1-0/+6
2025-05-29AMDGPU: Remove redundant operand folding checks (#140587)Matt Arsenault1-18/+0
2025-05-29AMDGPU: Delete seemingly dead s_fmaak_f32/s_fmamk_f32 folding code (#140580)Matt Arsenault1-11/+0
2025-05-27[AMDGPU] SIFoldOperands: Delay foldCopyToVGPROfScalarAddOfFrameIndex (#141558)Fabian Ritter1-5/+8
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi1-2/+1
2025-05-19AMDGPU: Check for subreg match when folding through reg_sequence (#140582)Matt Arsenault1-8/+40
2025-05-17AMDGPU: Move reg_sequence splat handling (#140313)Matt Arsenault1-46/+109
2025-05-08[AMDGPU][NFC] Remove unused operand types. (#139062)Ivan Kosarev1-2/+1
2025-05-05[AMDGPU] Handle MachineOperandType global address in SIFoldOperands. (#135424)Akhilesh Moorthy1-1/+7
2025-05-04[Target] Remove unused local variables (NFC) (#138443)Kazu Hirata1-1/+0
2025-04-30[AMDGPU] Fix register class constraints for si-fold-operands pass when foldin...mssefat1-0/+10
2025-04-22[AMDGPU] Do not fold COPY with implicit operands (#136003)Mariusz Sikora1-1/+2
2025-04-19[AMDGPU] Construct SmallVector with iterator ranges (NFC) (#136415)Kazu Hirata1-9/+6
2025-04-02[AMDGPU][True16][CodeGen] fold clamp update for true16 (#128919)Brox Chen1-1/+7
2025-04-02[AMDGPU][True16][CodeGen] Implement sgpr folding in true16 (#128929)Brox Chen1-4/+84
2025-04-01[AMDGPU] Fix SIFoldOperandsImpl::tryFoldZeroHighBits when met non-reg src1 op...Valery Pykhtin1-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-19 06:36:18 +0000