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path: root/llvm/lib/Target/AMDGPU/GCNSubtarget.h
AgeCommit message (Expand)AuthorFilesLines
2026-01-13[AMDGPU]Add specific instruction feature for multicast load (#175503)Shoreshen1-0/+3
2026-01-09[AMDGPU] Handle `s_setreg_imm32_b32` targeting `MODE` register (#174681)Shilei Tian1-0/+3
2026-01-09[AMDGPU] Add support for GFX12 expert scheduling mode 2 (#170319)Jay Foad1-0/+5
2026-01-07[AMDGPU] Improve llvm.amdgcn.wave.shuffle handling for pre-GFX8 (#174845)saxlungs1-0/+4
2026-01-06Reland "[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic (#167372)" (#174614)saxlungs1-0/+6
2026-01-05Revert "[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic" (#174501)Joe Nash1-6/+0
2026-01-05[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic (#167372)saxlungs1-0/+6
2025-12-18[AMDGPU] Remove trivially true predicates from GCNSubtarget. NFC. (#172830)Jay Foad1-28/+0
2025-12-10[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)Mirko BrkuĊĦanin1-0/+4
2025-12-05AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)anjenner1-0/+4
2025-12-02[AMDGPU] Prevent folding of flat_scr_base_hi into a 64-bit SALU (#170373)Stanislav Mekhanoshin1-0/+6
2025-11-25[AMDGPU][gfx1250] Add wait_xcnt before any access that cannot be repeated (#1...Pierre van Houtryve1-3/+6
2025-11-19[AMDGPU] Adding instruction specific features (#167809)Shoreshen1-0/+21
2025-11-18[NFC] Check operand type instead of opcode (#168641)Shilei Tian1-1/+1
2025-11-18[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its...Shilei Tian1-0/+7
2025-11-12CodeGen: Remove target hook for terminal rule (#165962)Matt Arsenault1-2/+0
2025-11-10RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)Matt Arsenault1-0/+2
2025-10-27[AMDGPU] Add target feature for waits before system scope stores. NFC. (#164993)Jay Foad1-0/+5
2025-10-22[AMDGPU] Add intrinsics for v_[pk]_add_{min|max}_* instructions (#164731)Stanislav Mekhanoshin1-2/+4
2025-10-20AMDGPU: Remove triple field from subtarget (#164208)Matt Arsenault1-1/+0
2025-10-06[NFC] Change spelling of cluster feature to "clusters" (#162103)Shilei Tian1-2/+2
2025-10-06[AMDGPU] Make cluster a target feature (#162040)Shilei Tian1-1/+3
2025-09-25AMDGPU: Ensure both wavesize features are not set (#159234)Matt Arsenault1-0/+1
2025-09-24[AMDGPU] Add the support for 45-bit buffer resource (#159702)Shilei Tian1-0/+8
2025-09-16[AMDGPU] Use larger immediate values in S_NOP (#158990)Jay Foad1-0/+10
2025-09-10[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)Pierre van Houtryve1-0/+3
2025-09-10Revert "[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)" (#157639)Pierre van Houtryve1-3/+0
2025-09-10[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)Pierre van Houtryve1-0/+4
2025-09-02[AMDGPU] Add s_set_vgpr_msb gfx1250 instruction (#156524)Stanislav Mekhanoshin1-0/+3
2025-08-26AMDGPU: Add target feature for aligned VGPR requirement (#155336)Matt Arsenault1-1/+2
2025-08-15[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register (#153879)Stanislav Mekhanoshin1-0/+4
2025-08-15[AMDGPU] w/a hazard with writing s102/103 and reading FLAT_SCRATCH_BASE (#153...Stanislav Mekhanoshin1-0/+6
2025-08-15[AMDGPU] Mitigate DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 bug (#153872)Stanislav Mekhanoshin1-0/+6
2025-08-15[AMDGPU] Handle S_GETREG_B32 hazard on gfx1250 (#153848)Stanislav Mekhanoshin1-0/+4
2025-08-15[AMDGPU] gfx1250 does not need nop before VGPR dealloc (#153844)Stanislav Mekhanoshin1-5/+1
2025-08-14[AMDGPU] Enable kernarg preload on gfx1250 (#153686)Stanislav Mekhanoshin1-0/+6
2025-08-14[AMDGPU] Remove wave64 functions (#153690)Stanislav Mekhanoshin1-0/+4
2025-08-14[AMDGPU] Don't allow wgp mode on gfx1250 (#153680)Stanislav Mekhanoshin1-1/+5
2025-08-06[AMDGPU] s_get_shader_cycles_u64 gfx1250 instruction (#152390)Stanislav Mekhanoshin1-0/+3
2025-08-06[AMDGPU] gfx1250 has fixed GETPC bug and also extended VA to 57 bits (#152373)Stanislav Mekhanoshin1-2/+3
2025-08-06[AMDGPU] System scope atomics are emulated over PCIe in gfx1250 (#152369)Stanislav Mekhanoshin1-0/+7
2025-08-06[AMDGPU] Support 64-bit LDS atomic fadd on gfx1250 (#152368)Stanislav Mekhanoshin1-1/+1
2025-08-05[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)Stanislav Mekhanoshin1-0/+5
2025-08-01[AMDGPU] gfx1250 v_perm_pk16_* instructions (#151773)Stanislav Mekhanoshin1-0/+3
2025-08-01[AMDGPU] Support function attribute to override postRA scheduling direction (...Harrison Hao1-0/+3
2025-07-30[AMDGPU] Add gfx1250 V_ADD_{MIN|MAX}_{U|I}32 instructions (#151379)Stanislav Mekhanoshin1-0/+3
2025-07-29[AMDGPU] gfx1250 V_{MIN|MAX}_{I|U}64 opcodes (#151256)Stanislav Mekhanoshin1-0/+3
2025-07-29[AMDGPU] Implement v_mad_u32/v_mad_nc_u|i64_u32 on gfx1250 (#151226)Stanislav Mekhanoshin1-0/+8
2025-07-29[AMDGPU] Support f64 atomics on gfx1250 (#151172)Changpeng Fang1-1/+3
2025-07-29[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)Pierre van Houtryve1-0/+3
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