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path: root/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault1-1/+1
2025-09-03AMDGPU: Avoid directly using MCOperandInfo RegClass field (#156641)Matt Arsenault1-12/+2
2025-09-02[AMDGPU] Fix a warningKazu Hirata1-1/+1
2025-09-03AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (#155595)Matt Arsenault1-16/+25
2025-08-11[AMDGPU] Per-subtarget DPP instruction classification (#153096)Stanislav Mekhanoshin1-5/+25
2025-08-11[AMDGPU] Fix DPP combining into V_BITOP3_B32 (#153083)Stanislav Mekhanoshin1-0/+5
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi1-2/+1
2025-04-19[AMDGPU] Construct SmallVector with iterator ranges (NFC) (#136415)Kazu Hirata1-5/+2
2025-03-31[AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918)Brox Chen1-0/+5
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi1-4/+2
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-1/+1
2024-09-03[AMDGPU][NewPM] Have consistent property changes in GCNDPPCombine (#106520)Akshat Oke1-2/+2
2024-08-29AMDGPU/NewPM Port GCNDPPCombine to NPM (#105816)Akshat Oke1-14/+41
2024-05-02[AMDGPU] Support byte_sel modifier for v_cvt_f32_fp8 and v_cvt_f32_bf8 (#90887)Stanislav Mekhanoshin1-1/+2
2024-04-26[AMDGPU] Support byte_sel modifier on v_cvt_sr_fp8_f32 and v_cvt_sr_bf8_f32 (...Stanislav Mekhanoshin1-0/+5
2024-01-25[AMDGPU] Fix warnings about unused variables [NFC]Mikael Holmen1-4/+2
2024-01-23[AMDGPU] Properly check op_sel in GCNDPPCombine (#79122)Mirko Brkušanin1-8/+20
2023-09-29[AMDGPU] Fix -Wunused-function in GCNDPPCombine.cpp (NFC)Jie Fu1-1/+1
2023-09-29[AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on supported subtargets (#...Mirko Brkušanin1-1/+22
2023-08-22[AMDGPU] Rename 64BitDPP feature and fix the checksStanislav Mekhanoshin1-2/+2
2023-01-11[AMDGPU] Use MCInstrDesc::getSize. NFC.Jay Foad1-1/+1
2022-11-08[AMDGPU] Add & use `hasNamedOperand`, NFCPierre van Houtryve1-15/+9
2022-10-28[AMDGPU] Clean up calls to MachineOperand::setIsDead and friends. NFC.Jay Foad1-1/+1
2022-09-20[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,CJoe Nash1-0/+6
2022-08-28[Target] Qualify auto in range-based for loops (NFC)Kazu Hirata1-1/+1
2022-08-18[AMDGPU] Update comment on shrinking dpp. NFCJoe Nash1-3/+4
2022-07-30[AMDGPU] Fix || vs && precedence warning. NFC.Simon Pilgrim1-4/+4
2022-07-20[NFC] Suppress unused variable warning in non-assert buildsArthur Eubanks1-0/+1
2022-07-20[AMDGPU] NFC. Assert that mask is full with VOPC DPPJoe Nash1-1/+12
2022-07-19[AMDGPU] Remove old operand from VOPC DPPJoe Nash1-0/+5
2022-07-05[AMDGPU] gfx11 CodeGen for new DPP instructionsJoe Nash1-17/+110
2022-05-05[AMDGPU] Combine DPP mov even if old reg def is in different BBJay Foad1-6/+0
2022-03-11[AMDGPU] Support v_mov_b64 in dpp combineStanislav Mekhanoshin1-3/+9
2021-11-03[AArch64, AMDGPU] Use make_early_inc_range (NFC)Kazu Hirata1-2/+1
2021-04-20[AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is usedJay Foad1-0/+7
2021-04-19[AMDGPU] GCNDPPCombine: simplify API of isShrinkable. NFC.Jay Foad1-9/+10
2021-03-23[AMDGPU] Refactor DPPCombineJoe Nash1-42/+50
2021-02-17[AMDGPU] gfx90a supportStanislav Mekhanoshin1-12/+38
2021-01-20[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargetsdfukalov1-1/+2
2021-01-07[NFC][AMDGPU] Reduce include files dependency.dfukalov1-13/+0
2020-07-16AMDGPU: Rename add/sub with carry out instructionsMatt Arsenault1-4/+4
2020-07-03[AMDGPU] Don't combine DPP if DPP register is used more than once per instruc...vpykhtin1-5/+21
2020-06-29AMDGPU: Use IsSSA property check instead of asserting on isSSAMatt Arsenault1-2/+5
2020-05-27AMDGPU: Fix dropping MI flags when rewriting instructionsMatt Arsenault1-1/+3
2019-11-20[AMDGPU][DPP] Corrected DPP combinerDmitry Preobrazhensky1-6/+9
2019-10-25[AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (wh...vpykhtin1-1/+2
2019-10-16[AMDGPU] Do not combine dpp mov reading physregsStanislav Mekhanoshin1-0/+6
2019-10-16[AMDGPU] Do not combine dpp with physreg defStanislav Mekhanoshin1-0/+4
2019-10-15[AMDGPU] Support mov dpp with 64 bit operandsStanislav Mekhanoshin1-0/+7
2019-10-15[AMDGPU] Allow DPP combiner to work with REG_SEQUENCEStanislav Mekhanoshin1-5/+54
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