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path: root/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-01-03[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)Jun Wang1-0/+25
2024-11-25AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)Matt Arsenault1-0/+8
2024-11-25AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#117592)Matt Arsenault1-0/+1
2024-11-25AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)Matt Arsenault1-0/+1
2024-11-23AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)Matt Arsenault1-8/+8
2024-11-23AMDGPU: Move default wavesize hack for disassembler (#117422)Matt Arsenault1-18/+2
2024-11-21AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)Matt Arsenault1-0/+75
2024-11-20[AMDGPU][MC][True16] Support VOP2 instructions with true16 format (#115233)Brox Chen1-0/+19
2024-11-14[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (#113634)Brox Chen1-8/+30
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-18/+18
2024-09-28[AMDGPU] Use MCRegister. NFCCraig Topper1-7/+7
2024-09-24[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)Jun Wang1-0/+1
2024-09-20[AMDGPU] Do not use APInt for simple 64-bit arithmetic. NFC. (#109414)Jay Foad1-4/+2
2024-09-11[AMDGPU][True16][MC] 16bit vsrc and vdst support in MC (#104510)Brox Chen1-8/+14
2024-08-26[MC] Update MCOperand::getReg/setReg/createReg and MCInstBuilder::addReg to u...Craig Topper1-1/+1
2024-07-17[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)Jay Foad1-12/+10
2024-07-16[AMDGPU] Remove wavefrontsize feature from GFX10+ (#98400)Stanislav Mekhanoshin1-2/+18
2024-07-07[AMDGPU][MC] Allow UC_VERSION_* constant reuse (#96461)Carl Ritson1-2/+10
2024-06-27[AMDGPU] Only reinitialize disassembler Bytes array when needed. NFC. (#96666)Jay Foad1-6/+6
2024-06-18[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)Ivan Kosarev1-0/+59
2024-05-04Add clarifying parenthesis around non-trivial conditions in ternary expressio...luolent1-2/+2
2024-04-26[AMDGPU] Support byte_sel modifier on v_cvt_sr_fp8_f32 and v_cvt_sr_bf8_f32 (...Stanislav Mekhanoshin1-8/+0
2024-04-18 [AMDGPU] Add disassembler diagnostics for invalid kernel descriptors (#87400)Emma Pilkington1-89/+159
2024-02-26[AMDGPU] Only try DecoderTables for the current subtarget. NFCI. (#82992)Jay Foad1-15/+30
2024-02-23[AMDGPU] Simplify AMDGPUDisassembler::getInstruction by removing Res. (#82775)Jay Foad1-142/+110
2024-02-22[AMDGPU] Remove DPP DecoderNamespaces. NFC. (#82491)Jay Foad1-52/+5
2024-02-22[AMDGPU] Clean up conversion of DPP instructions in AMDGPUDisassembler (#82480)Jay Foad1-74/+53
2024-02-22[AMDGPU] Split Dpp8FI and Dpp16FI operands (#82379)Jay Foad1-20/+13
2024-02-20[AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (#82233)Jay Foad1-12/+1
2024-02-20[AMDGPU] Try decoding instructions longest first. NFCI. (#82014)Jay Foad1-42/+42
2024-02-19[AMDGPU] Fix decoder for BF16 inline constants (#82276)Stanislav Mekhanoshin1-34/+76
2024-02-17[AMDGPU] Set predicates more consistently for BUF instructions (#81865)Jay Foad1-3/+0
2024-02-15[AMDGPU] Use consistent DecoderNamespace for wave64 instructions. NFC. (#81863)Jay Foad1-2/+2
2024-02-13[AMDGPU][NFC] Get rid of some operand decoders defined using macros. (#81482)Ivan Kosarev1-59/+25
2024-02-08[AMDGPU][True16] Support VOP3 source DPP operands. (#80892)Ivan Kosarev1-0/+38
2024-02-01[llvm-objdump][AMDGPU] Pass ELF ABIVersion through disassembler (#78907)Emma Pilkington1-3/+7
2024-01-26Fix MSVC "signed/unsigned mismatch" warning. NFC.Simon Pilgrim1-1/+1
2024-01-25[AMDGPU][NFC] Use templates to decode AV operands. (#79313)Ivan Kosarev1-16/+28
2024-01-24[AMDGPU][NFC] Simplify AGPR/VGPR load/store operand definitions. (#79289)Ivan Kosarev1-38/+10
2024-01-24[AMDGPU] Add GFX12 WMMA and SWMMAC instructions (#77795)Mirko Brkušanin1-0/+8
2024-01-24[AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (#78...Mariusz Sikora1-0/+26
2024-01-21[AMDGPU] Add an asm directive to track code_object_version (#76267)Emma Pilkington1-1/+2
2024-01-18[AMDGPU] Add global_load_tr for GFX12 (#77772)Piotr Sobczak1-0/+4
2024-01-04AMDGPU: Fix packed 16-bit inline constants (#76522)Nicolai Hähnle1-0/+6
2024-01-02[AMDGPU] Update compute program resource registers for GFX12 (#75911)Jay Foad1-13/+39
2023-12-28[AMDGPU][True16] Don't use the VGPR_LO/HI16 register classes. (#76440)Ivan Kosarev1-3/+2
2023-12-21[AMDGPU] Remove GDS and GWS for GFX12 (#76148)Jay Foad1-0/+5
2023-12-15[AMDGPU] Add pseudo scalar trans instructions for GFX12 (#75204)Mirko Brkušanin1-0/+1
2023-12-15[AMDGPU][MC] Add GFX12 SMEM encoding (#75215)Mirko Brkušanin1-0/+3
2023-12-13[AMDGPU] GFX12: Add Split Workgroup Barrier (#74836)Mariusz Sikora1-0/+11
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