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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-06-27AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)Matt Arsenault1-0/+3
2025-06-23AMDGPU: Remove legacy pass manager version of AMDGPUAttributor (#145262)Matt Arsenault1-1/+0
2025-06-22AMDGPU: Use reportFatalUsageError for regalloc flag error (#145198)Matt Arsenault1-2/+2
2025-06-21AMDGPU: Really delete AMDGPUAnnotateKernelFeatures (#145136)Matt Arsenault1-3/+0
2025-06-20AMDGPU: Remove legacy pass manager version of AMDGPUUnifyMetadata (#144985)Matt Arsenault1-1/+0
2025-06-20AMDGPU: Remove legacy PM version of AMDGPUPromoteAllocaToVector (#144986)Matt Arsenault1-1/+0
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+2
2025-06-05[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)Diana Picus1-1/+3
2025-06-03[MISched] Add templates for creating custom schedulers (#141935)Pengcheng Wang1-1/+1
2025-05-30Reapply "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer ...Shilei Tian1-0/+4
2025-05-30Revert "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer k...Shilei Tian1-4/+0
2025-05-30Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel ar...Shilei Tian1-0/+4
2025-05-30Revert "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arg...Shilei Tian1-4/+0
2025-05-30[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (...Shilei Tian1-0/+4
2025-05-29[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#13...Shilei Tian1-6/+22
2025-05-26[AMDGPU] Cluster export instructions in PostRA Scheduler (#141399)Carl Ritson1-0/+1
2025-05-19[AMDGPU] Set AS8 address width to 48 bitsAlexander Richardson1-4/+3
2025-05-11[AMDGPU] Move kernarg preload logic to separate pass (#130434)Austin Kerbow1-0/+8
2025-05-06Register assembly printer passes (#138348)Matthias Braun1-0/+1
2025-05-02[AMDGPU][Attributor] Add `ThinOrFullLTOPhase` as an argument (#123994)Shilei Tian1-3/+6
2025-04-30[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)Akshat Oke1-0/+46
2025-04-26[TTI] Simplify implementation (NFCI) (#136674)Sergei Barannikov1-1/+1
2025-04-21[AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (#136...Christudasan Devadasan1-5/+3
2025-04-17[AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (#130071)Akshat Oke1-0/+1
2025-04-15[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)Jun Wang1-7/+0
2025-04-15[HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (#134753)Alex Voicu1-7/+13
2025-04-14[CodeGen][NPM] Port BranchRelaxation to NPM (#130067)Akshat Oke1-1/+2
2025-04-11[AMDGPU] Teach iterative schedulers about IGLP (#134953)Jeffrey Byrnes1-2/+6
2025-04-10[AMDGPU] Make the iterative schedulers selectable via amdgpu-sched-strategy (...Jeffrey Byrnes1-0/+9
2025-04-09[CodeGen][NPM] Port PostRAHazardRecognizer to NPM (#130066)Akshat Oke1-1/+2
2025-04-08[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)Akshat Oke1-4/+3
2025-04-07[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)Rahul Joshi1-0/+2
2025-04-02[AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM (#130064)Akshat Oke1-3/+2
2025-03-26[AMDGPU][NPM] Port SILateBranchLowering to NPM (#130063)Akshat Oke1-2/+3
2025-03-25[AMDGPU][NPM] Port SIInsertHardClauses to NPM (#130062)Akshat Oke1-1/+1
2025-03-24[AMDGPU][NPM] Port SIInsertWaitcnts to NPM (#130061)Akshat Oke1-2/+2
2025-03-19[AMDGPU][NPM] Port AMDGPUMarkLastScratchLoad to NPM (#131738)Akshat Oke1-1/+1
2025-03-14[NFC][AMDGPU] Replace direct arch comparison with `isAMDGCN()` (#131357)Shilei Tian1-11/+9
2025-03-14[AMDGPU][NPM] Port GCNCreateVOPD to NPM (#130059)Akshat Oke1-2/+2
2025-03-12AMDGPU/GlobalISel: Disable LCSSA pass (#124297)Petar Avramovic1-2/+8
2025-03-12[AMDGPU][NPM] Port SIMemoryLegalizer to NPM (#130060)Akshat Oke1-2/+3
2025-03-10AMDGPU: Move enqueued block handling into clang (#128519)Matt Arsenault1-5/+5
2025-03-10[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)Akshat Oke1-3/+4
2025-03-04[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)Akshat Oke1-1/+1
2025-02-26[AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (#128003)Akshat Oke1-1/+41
2025-02-21[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)Akshat Oke1-2/+3
2025-02-20[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)Akshat Oke1-1/+2
2025-02-18[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)Vikram Hegde1-1/+8
2025-02-17[AMDGPU] Push amdgpu-preload-kern-arg-prolog after livedebugvalues (#126148)Scott Linder1-0/+6
2025-02-17[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)Vikram Hegde1-1/+2
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