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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
AgeCommit message (Expand)AuthorFilesLines
2026-01-11[TargetLowering] Change the `softPromoteHalfType` default to `true` (#175149)Trevor Gross1-0/+2
2025-12-16[CodeGen] expand-fp: Change frem expansion criterion (#158285)Frederik Harwath1-1/+0
2025-12-05AMDGPU: Improve exp10 lowering for f16 (#170771)Matt Arsenault1-0/+3
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault1-1/+2
2025-11-17[AMDGPU] TableGen-erate SDNode descriptions (#168248)Sergei Barannikov1-231/+0
2025-09-23Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)Janek van Oirschot1-3/+0
2025-09-16[AMDGPU] Elide bitcast fold i64 imm to build_vector (#154115)Janek van Oirschot1-0/+3
2025-09-04[AMDGPU] Tail call support for whole wave functions (#145860)Diana Picus1-0/+1
2025-08-22[AMDGPU] canCreateUndefOrPoisonForTargetNode - BFE_I32/U32 can't create poiso...Simon Pilgrim1-0/+6
2025-08-05[LLVM][CGP] Allow finer control for sinking compares. (#151366)Paul Walker1-0/+10
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus1-0/+6
2025-07-15[AMDGPU] gfx1250 64-bit relocations and fixups (#148951)Stanislav Mekhanoshin1-0/+1
2025-05-08AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (#128911)Brox Chen1-0/+3
2025-04-23[DAG] shouldReduceLoadWidth - add optional<unsigned> byte offset argument (#1...Simon Pilgrim1-3/+2
2025-04-18[DAG] isKnownNeverNaN - add DemandedElts element mask to isKnownNeverNaN call...Simon Pilgrim1-3/+2
2025-03-29[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)Tim Gymnich1-1/+1
2025-03-20[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)Diana Picus1-0/+1
2025-03-18[CodeGen][GlobalISel] Add a getVectorIdxWidth and getVectorIdxLLT. (#131526)David Green1-1/+1
2024-12-21[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119...Sergei Barannikov1-2/+4
2024-11-11[AMDGPU] Remove unused AMDGPUISD enum members (NFC) (#115582)Sergei Barannikov1-9/+0
2024-10-09[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)Jeffrey Byrnes1-3/+0
2024-09-19[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)Pierre van Houtryve1-1/+1
2024-09-06[AMDGPU] Add target intrinsic for s_buffer_prefetch_data (#107293)Stanislav Mekhanoshin1-0/+1
2024-08-29AMDGPU: Use pattern to select instruction for intrinsic llvm.fptrunc.round (#...Changpeng Fang1-1/+0
2024-08-17AMDGPU: Add tonearest and towardzero roundings for intrinsic llvm.fptrunc.rou...Changpeng Fang1-2/+1
2024-08-08AMDGPU: Directly handle all atomicrmw cases in SIISelLowering (#102439)Matt Arsenault1-2/+0
2024-06-18AMDGPU: Support local atomicrmw fmin/fmax for float/double (#95590)Matt Arsenault1-2/+0
2024-06-17AMDGPU: Remove .v2bf16 buffer atomic fadd intrinsics (#95783)Matt Arsenault1-1/+0
2024-05-27[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)Mirko BrkuĊĦanin1-0/+5
2024-05-07AMDGPU: Don't bitcast float typed atomic store in IR (#90116)Matt Arsenault1-0/+4
2024-05-07AMDGPU: Do not bitcast atomicrmw in IR (#90045)Matt Arsenault1-0/+4
2024-04-26AMDGPU: Do not bitcast atomic load in IR (#90060)Matt Arsenault1-0/+6
2024-04-24[AMDGPU] Add a trap lowering workaround for gfx11 (#85854)Emma Pilkington1-0/+3
2024-01-19[AMDGPU] Remove unnecessary add instructions in ctlz.i8 (#77615)Leon Clark1-0/+2
2024-01-18[AMDGPU][GFX12] Add 16 bit atomic fadd instructions (#75917)Mariusz Sikora1-0/+1
2024-01-17[AMDGPU][GFX12] Add Atomic cond_sub_u32 (#76224)Mariusz Sikora1-0/+1
2024-01-17[AMDGPU] CodeGen for GFX12 8/16-bit SMEM loads (#77633)Jay Foad1-0/+4
2023-12-13[AMDGPU] Min/max changes for GFX12 (#75214)Piotr Sobczak1-0/+2
2023-12-02AMDGPU: Support llvm.exp10 (#65860)Matt Arsenault1-0/+2
2023-11-06[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)Diana1-0/+1
2023-09-27[GlobalISel] Remove TargetLowering::isConstantUnsignedBitfieldExtractLegalJay Foad1-3/+0
2023-09-12AMDGPU: Correctly lower llvm.sqrt.f32Matt Arsenault1-0/+3
2023-08-15AMDGPU: Fix fast f32 log/log10Matt Arsenault1-1/+1
2023-08-11AMDGPU: Handle llvm.stacksave and llvm.stackrestoreMatt Arsenault1-3/+5
2023-07-05AMDGPU: Correctly lower llvm.exp.f32Matt Arsenault1-0/+3
2023-07-05AMDGPU: Correctly lower llvm.exp2.f32Matt Arsenault1-0/+1
2023-07-05AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32Matt Arsenault1-2/+12
2023-06-23AMDGPU: Use correct lowering for llvm.log2.f32Matt Arsenault1-0/+1
2023-06-15AMDGPU: Add llvm.amdgcn.exp2 intrinsicMatt Arsenault1-0/+3
2023-06-12AMDGPU: Add llvm.amdgcn.log intrinsicMatt Arsenault1-0/+4
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