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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2026-01-08AMDGPU: Teach lowering that sqrt never returns subnormal (#174838)Matt Arsenault1-0/+2
2025-12-28[CodeGen] Fix EVT::changeVectorElementType assertion on simple-to-extended fa...Islam Imad1-6/+3
2025-12-23AMDGPU: Teach lowering that exp and log intrinsics cannot return denormals (#...Matt Arsenault1-0/+5
2025-12-08AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)Matt Arsenault1-0/+1
2025-12-08[AMDGPU] Common up some unsafe fexp lowering. NFC. (#170841)Jay Foad1-14/+7
2025-12-05[AMDGPU] Make rotr illegal (#166558)Jay Foad1-3/+1
2025-12-05AMDGPU: Improve exp10 lowering for f16 (#170771)Matt Arsenault1-13/+26
2025-12-04[AMDGPU] Update log lowering to remove contract for AMDGCN backend (#168916)Adel Ejjeh1-3/+6
2025-12-04AMDGPU: Create a dummy call sequence when emitting call error (#170656)Matt Arsenault1-1/+6
2025-12-04AMDGPU: Use correct chain when emitting error on a call (#170645)Matt Arsenault1-1/+1
2025-12-04AMDGPU: Fix broken exp10 lowering for f16 (#170582)Matt Arsenault1-3/+7
2025-11-24[AMDGPU] Propagate AA info in vector load/store splitting. (#168871)Leon Clark1-11/+11
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault1-2/+3
2025-11-17[AMDGPU] TableGen-erate SDNode descriptions (#168248)Sergei Barannikov1-163/+1
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad1-1/+1
2025-11-06[CodeGen] Delete two ComputeValueVTs overloads (NFC) (#166758)Sergei Barannikov1-1/+2
2025-10-23[AMDGPU][NFC] Cleanly make 32-bit abs legal (#164837)LU-JOHN1-2/+2
2025-10-17[AMDGPU] 32-bit ABS is a legal DAG node (#163907)LU-JOHN1-2/+2
2025-10-13[AMDGPU] Remove NoInfsFPMath uses (#163028)paperchalice1-4/+3
2025-09-23Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)Janek van Oirschot1-28/+0
2025-09-16[AMDGPU] Elide bitcast fold i64 imm to build_vector (#154115)Janek van Oirschot1-0/+28
2025-09-11[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit w...Chris Jackson1-4/+2
2025-09-04[AMDGPU] Tail call support for whole wave functions (#145860)Diana Picus1-0/+1
2025-09-03[AMDGPU] Implement IR expansion for frem instruction (#130988)Frederik Harwath1-18/+3
2025-09-02[CG] Add VTs for v[567]i1 and v[567]f16 (#156523)Adam Nemet1-0/+12
2025-08-28[AMDGPU] Remove `ApproxFuncFPMath` uses (#155578)paperchalice1-6/+2
2025-08-22[AMDGPU] canCreateUndefOrPoisonForTargetNode - BFE_I32/U32 can't create poiso...Simon Pilgrim1-0/+13
2025-08-20AMDGPU: Fix using illegal extract_subvector indexes (#154098)Matt Arsenault1-5/+25
2025-08-19[AMDGPU] upstream barrier count reporting part1 (#154409)Gang Chen1-0/+7
2025-08-18[AMDGPU] Combine prng(undef) -> undef (#154160)Stanislav Mekhanoshin1-1/+2
2025-08-05Revert "[CG] Add VTs for v[567]i1 and v[567]f16" (#152217)Adam Nemet1-12/+0
2025-08-05[LLVM][CGP] Allow finer control for sinking compares. (#151366)Paul Walker1-8/+0
2025-08-02[CG] Add VTs for v[567]i1 and v[567]f16 (#151763)Adam Nemet1-0/+12
2025-07-31[AMDGPU] Remove `UnsafeFPMath` uses (#151079)paperchalice1-3/+3
2025-07-28[NFC][AMDGPU] Move cmp+select arguments optimization to SIISelLowering. (#150...Daniil Fukalov1-83/+0
2025-07-28[CodeGen] More consistently expand float ops by default (#150597)Nikita Popov1-4/+6
2025-07-21[AMDGPU] Remove some duplicated lines. NFC. (#128029)Jay Foad1-1/+0
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus1-0/+4
2025-07-16[AMDGPU] Try to reuse register with the constant from compare in v_cndmask (#...Daniil Fukalov1-0/+83
2025-07-15[AMDGPU] gfx1250 64-bit relocations and fixups (#148951)Stanislav Mekhanoshin1-0/+1
2025-07-14[AMDGPU] Add support for `v_tanh_bf16` on gfx1250 (#147425)Shilei Tian1-2/+4
2025-07-09[AMDGPU] Create hi-half of 64-bit ashr with mov of -1 (#146569)LU-JOHN1-3/+10
2025-07-08[DAG] Add generic expansion for ISD::FCANONICALIZE nodes (#142105)Dominik Steenken1-0/+5
2025-07-07[AMDGPU] Preserve exact flag for lshr (#146744)LU-JOHN1-1/+2
2025-07-07[AMDGPU][NFC] Fix typo "store" -> "load" in comment for AMDGPUTLI::performLoa...Fabian Ritter1-1/+1
2025-06-26[AMDGPU] Convert 64-bit sra to 32-bit if shift amt >= 32 (#144421)LU-JOHN1-26/+87
2025-06-23AMDGPU: Use reportFatalUsageError for unhandled calling conventions (#145261)Matt Arsenault1-2/+2
2025-06-20AMDGPU: Remove AMDGPUInstrInfo class (#144984)Matt Arsenault1-1/+1
2025-06-13[AMDGPU] Convert more 64-bit lshr to 32-bit if shift amt>=32 (#138204)LU-JOHN1-39/+91
2025-05-30[AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (#138913)LU-JOHN1-14/+9
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