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2026-01-12[AArch64] Add support for range prefetch intrinsic (#170490)Kerry McLaughlin1-0/+8
2026-01-09XCOFF associated metadata (#159096)Sean Fertile1-0/+25
2026-01-07[NVPTX][AutoUpgrade] Use integer min/max intrinsics instead of icmp, select (...Alex MacLean1-22/+13
2026-01-07Reapply "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674) (...Shilei Tian1-0/+57
2026-01-07Revert "[AMDGPU] Rework the clamp support for WMMA instructions" (#174674)dyung1-57/+0
2026-01-06[AMDGPU] Rework the clamp support for WMMA instructions (#174310)Shilei Tian1-0/+57
2026-01-06[IR] Split vector.splice into vector.splice.left and vector.splice.right (#17...Luke Lau3-14/+51
2026-01-05[OptBisect][ADT] Add support for running ranges of passes and introduce Integ...Yonah Goldberg1-7/+52
2026-01-04Revert "[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)"...Shilei Tian1-32/+0
2026-01-04[IR] Reland Optimize PHINode::removeIncomingValue() and PHINode::removeIncomi...Mingjie Xu1-24/+17
2026-01-02[IRBuilder] Introduce CreateSelectFMFWithUnknownProfile (#174162)Aiden Grossman1-0/+11
2026-01-01[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)Srinivasa Ravi1-0/+71
2025-12-29Revert 159f1c048e08a8780d92858cfc80e723c90235e3 (#173893)Walter Lee1-17/+24
2025-12-27[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)Muhammad Abdul1-0/+32
2025-12-26[SLP]Enable float point math ops as copyables elements.Alexey Bataev1-0/+7
2025-12-26Revert "[SLP]Enable float point math ops as copyables elements."Alexey Bataev1-7/+0
2025-12-25[SLP]Enable float point math ops as copyables elements.Alexey Bataev1-0/+7
2025-12-25[LV][IRBuilder] Allow implicit truncation of step vector (#173229)Nikita Popov1-1/+3
2025-12-25[IR] Change PHINode::removeIncomingValueIf() to loop incoming values backward...Mingjie Xu1-4/+3
2025-12-22[IR] Fix User use-after-destroy by zapping in ~User (#170575)Reid Kleckner1-26/+43
2025-12-23[IR] Value::setNameImpl: fix use-after-free when new name aliases old storage...Wenju He1-6/+13
2025-12-22Revert "[SLP]Enable float point math ops as copyables elements."Alexey Bataev1-7/+0
2025-12-22[IR][Verifier] Verification for `target-features` attribute (#173119)Stefan Weigl-Bosker1-0/+16
2025-12-21[SLP]Enable float point math ops as copyables elements.Alexey Bataev1-0/+7
2025-12-19[AutoUpgrade]: Fixed assertion by considering number of args (#172911)Kevin Per1-3/+7
2025-12-18[MemProf] Update metadata verification for a single string tag (#172543)Teresa Johnson1-11/+4
2025-12-18[NVPTX] Add support for barrier.cta.red.* instructions (#172541)Alex MacLean1-0/+18
2025-12-18[IR] Update `PHINode::removeIncomingValueIf()` to use the swap strategy like ...Mingjie Xu1-17/+13
2025-12-17[IR] Optimize PHINode::removeIncomingValue() by swapping removed incoming val...Mingjie Xu1-8/+6
2025-12-14[IR] Optimize PHINode::removeIncomingValueIf() using two-pointer (#171961)Mingjie Xu1-17/+16
2025-12-11[IR] Don't store switch case values as operandsAlexis Engelke5-27/+49
2025-12-11DAG: Use RuntimeLibcalls to legalize vector frem calls (#170719)Matt Arsenault1-4/+49
2025-12-11IR: Stop requiring nsz to reassociate fmul (#171726)Matt Arsenault1-0/+1
2025-12-11[PowerPC][AIX] Specify correct ABI alignment for double (#144673)Nikita Popov1-1/+7
2025-12-11[Verifier] Make sure all constexprs in instructions are visited (#171643)Nikita Popov1-8/+5
2025-12-10[LLVM][IR] Add support for address space names in DataLayout (#170559)Rahul Joshi2-49/+134
2025-12-10[AMDGPU] Relax restrictions on amdgcn.cs.chain intrinsic (#169785)Diana Picus1-3/+7
2025-12-09AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)anjenner1-4/+7
2025-12-09[x86][AVX-VNNI] Fix VPDPWXXD Argument Types (#169456)BaiXilin1-30/+153
2025-12-09[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)Luke Lau1-3/+0
2025-12-08[llvm-c] Deprecate functions working on the global context (#163979)Nikita Popov1-28/+32
2025-12-08[IR] Add ImplicitTrunc argument to ConstantInt::get() (#170865)Nikita Popov1-6/+7
2025-12-06Revert "[IR] Don't store switch case values as operands" (#170962)Vitaly Buka4-42/+26
2025-12-05[NFC][LLVM] Minor code cleanup in DebugLoc (#170757)Rahul Joshi1-5/+3
2025-12-05[IR] Don't store switch case values as operands (#166842)Alexis Engelke4-26/+42
2025-12-05[IR] Fix vector.splice verifier scaling by vscale for fixed length vectors (#...Luke Lau1-1/+2
2025-12-04[llvm-c] Add LLVMConstFPFromBits() API (#164381)peter mckinna1-0/+8
2025-12-04[IR] Add CallBr intrinsics support (#133907)Robert Imschweiler1-5/+28
2025-12-04[llvm][DebugInfo] Allow DIDerivedType as a bound in DISubrangeType (#165880)Tom Tromey2-5/+12
2025-12-03[LLVM][Intrinsics] Adds an API to automatically resolve overload types (#169007)Rajat Bajpai2-23/+49
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