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2012-12-01misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick3-19/+25
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. llvm-svn: 169072
2012-12-01misched: Fix the DAG builder to handle an undef operand at ExitSU.Andrew Trick1-1/+2
Assertion failed: (VNI && "No value to read by operand") rdar://12790267. llvm-svn: 169071
2012-12-01misched: Fix LiveInterval update to better handle DebugVal.Andrew Trick1-1/+5
Assertion failed: (itr != mi2iMap.end() && "Instruction not found in maps.") rdar://12777252. llvm-svn: 169070
2012-12-01misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick1-0/+2
assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. llvm-svn: 169069
2012-12-01Simplify REG_SEQUENCE lowering.Jakob Stoklund Olesen1-187/+69
The TwoAddressInstructionPass takes the machine code out of SSA form by expanding REG_SEQUENCE instructions into copies. It is no longer necessary to rewrite the registers used by a REG_SEQUENCE instruction because the new coalescer algorithm can do it now. REG_SEQUENCE is just converted to a sequence of sub-register copies now. llvm-svn: 169067
2012-11-30Add some first skeleton work for the DWARF5 Fission proposal. EmitEric Christopher2-8/+119
part of the compile unit CU and start separating out information into the various sections that will be pulled out later. WIP. llvm-svn: 169061
2012-11-30Convert COPY instructions into KILLs if they have implicit defs.Jakob Stoklund Olesen1-3/+17
MachineCopyPropagation doesn't understand super-register liveness well enough to be able to remove implicit defs of super-registers. This fixes a problem in ARM/2012-01-26-CopyPropKills.ll that is exposed by an future TwoAddressInstructionPass change. The KILL instructions are removed before the machine code is emitted. llvm-svn: 169060
2012-11-30Replace r168930 with a more reasonable patch.Bill Wendling2-3/+9
The original patch removed a bunch of code that the SjLjEHPrepare pass placed into the entry block if all of the landing pads were removed during the CodeGenPrepare class. The more natural way of doing things is to run the CGP *before* we run the SjLjEHPrepare pass. Make it so! llvm-svn: 169044
2012-11-29More comment.Eric Christopher1-0/+2
llvm-svn: 168952
2012-11-29Cleanup recent addition of DAGTypeLegalizer::SplitVecOp_VSELECTJustin Holewinski1-35/+31
llvm-svn: 168932
2012-11-29misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer1-0/+2
This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. llvm-svn: 168885
2012-11-29Teach the legalizer how to handle operands for VSELECT nodesJustin Holewinski2-1/+60
If we need to split the operand of a VSELECT, it must be the mask operand. We split the entire VSELECT operand with EXTRACT_SUBVECTOR. llvm-svn: 168883
2012-11-29Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski1-1/+1
computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
2012-11-29Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen6-15/+17
This saves a bit of memory. llvm-svn: 168852
2012-11-29Avoid rewriting instructions twice.Jakob Stoklund Olesen1-0/+9
This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). <rdar://problem/12758887> llvm-svn: 168837
2012-11-29When combining consecutive stores allow loads in between the stores, if the ↵Nadav Rotem1-3/+61
loads do not alias. llvm-svn: 168832
2012-11-28Make the LiveRegMatrix analysis available to targets.Jakob Stoklund Olesen20-564/+21
No functional change, just moved header files. Targets can inject custom passes between register allocation and rewriting. This makes it possible to tweak the register allocation before rewriting, using the full global interference checking available from LiveRegMatrix. llvm-svn: 168806
2012-11-28misched: Analysis that partitions the DAG into subtrees.Andrew Trick2-56/+222
This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
2012-11-28misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2-2/+2
llvm-svn: 168772
2012-11-28misched: better alias analysis.Andrew Trick1-2/+3
This fixes a hole in the "cheap" alias analysis logic implemented within the DAG builder itself, regardless of whether proper alias analysis is enabled. It now handles this pattern produced by LSR+CodeGenPrepare. %sunkaddr1 = ptrtoint * %obj to i64 %sunkaddr2 = add i64 %sunkaddr1, %lsr.iv %sunkaddr3 = inttoptr i64 %sunkaddr2 to i32* store i32 %v, i32* %sunkaddr3 llvm-svn: 168768
2012-11-28misched: Debug output fix. Use an always valid iterator.Andrew Trick1-1/+1
llvm-svn: 168767
2012-11-28Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.Jakob Stoklund Olesen3-691/+659
The *Impl class no longer serves a purpose now that the super-class implementation is in CodeGen. llvm-svn: 168759
2012-11-28Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen3-0/+338
The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
2012-11-28Revert r168630, r168631, and r168633 as these are causing nightly test failures.Chad Rosier4-2/+4
llvm-svn: 168751
2012-11-27Attempt to make the comments for dwarf debug look more likeEric Christopher2-274/+200
the coding standard would like. llvm-svn: 168737
2012-11-27Reapply section moving, make sure string section is output last.Eric Christopher1-24/+54
llvm-svn: 168736
2012-11-27CSE: allow PerformTrivialCoalescing to check copies across basic blockManman Ren1-2/+0
boundaries. Given the following case: BB0 %vreg1<def> = SUBrr %vreg0, %vreg7 %vreg2<def> = COPY %vreg7 BB1 %vreg10<def> = SUBrr %vreg0, %vreg2 We should be able to CSE between SUBrr in BB0 and SUBrr in BB1. rdar://12462006 llvm-svn: 168717
2012-11-27Remove duplicated #includes.Jakub Staszak1-4/+0
llvm-svn: 168712
2012-11-27Never use .lcomm on platforms where it does not accept an alignmentUlrich Weigand1-2/+7
argument. Instead, use a pair of .local and .comm directives. This avoids spurious differences between binaries built by the integrated assembler vs. those built by the external assembler, since the external assembler may impose alignment requirements on .lcomm symbols where the integrated assembler does not. llvm-svn: 168704
2012-11-27Revert rearrangement of debug info sections to unblock the botsEric Christopher1-59/+26
and O0 + debug codegen. llvm-svn: 168680
2012-11-27Remove unneeded #include.Jakub Staszak1-1/+0
llvm-svn: 168670
2012-11-27Remove unneeded #include.Jakub Staszak1-1/+0
llvm-svn: 168664
2012-11-27llvm/CodeGen: Remove empty files in r168659.NAKAMURA Takumi1-0/+0
llvm-svn: 168663
2012-11-27Remove unused forward declaration.Jakub Staszak1-1/+0
llvm-svn: 168660
2012-11-27Remove unused MachineLoopRanges analysis.Jakub Staszak4-149/+0
llvm-svn: 168659
2012-11-27Make comment names match function names.Eric Christopher1-3/+3
llvm-svn: 168644
2012-11-27Add in sections for the fission case (no change so incorrect) andEric Christopher1-1/+32
add a TODO for starting. llvm-svn: 168643
2012-11-27Reorder section output ordering.Eric Christopher1-25/+27
llvm-svn: 168638
2012-11-27Whitespace cleanup.Eric Christopher1-27/+27
llvm-svn: 168637
2012-11-26Add an assertion to ensure freezeReservedRegs() is only ever called once.Chad Rosier1-0/+2
llvm-svn: 168633
2012-11-26Now that the X86 Maximal Stack Alignment Check pass has been removed (i.e.,Chad Rosier2-3/+0
r168627), we no longer need to call the freezeReservedRegs() function a second time. Previously, this pass was conservatively adding the FP to the set of reserved registers, requiring the second update to the reserved registers. rdar://12719844 llvm-svn: 168631
2012-11-26Now that the X86 Maximal Stack Alignment Check pass has been removed (i.e.,Chad Rosier1-1/+0
r168627), we no longer need to call the freezeReservedRegs() function a second time. Previously, this pass was conservatively adding the FP to the set of reserved registers, requiring the second update to the reserved registers. rdar://12719844 llvm-svn: 168630
2012-11-26Don't use iterator after being erased.Jakub Staszak1-1/+1
llvm-svn: 168622
2012-11-26Remove unneeded #includes.Jakub Staszak1-4/+0
llvm-svn: 168608
2012-11-25Refactor to make helper method static.Craig Topper2-29/+14
llvm-svn: 168557
2012-11-25Remove duplicate check of LimitFloatPrecision. It was already checked ↵Craig Topper1-1/+1
earlier before IsExp10 could be set to true. llvm-svn: 168553
2012-11-25Factor common code out of individual if blocks into common tail.Craig Topper1-24/+12
llvm-svn: 168551
2012-11-24Remove redundant calls to getCurDebugLoc in visitIntrinsicCall. It's already ↵Craig Topper1-7/+4
called at the start of the function and captured in a local variable. llvm-svn: 168548
2012-11-24Refactor a bit to make some helper methods static.Craig Topper2-39/+20
llvm-svn: 168546
2012-11-24Factor some common code out of individual if blocks.Craig Topper1-52/+27
llvm-svn: 168538
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