aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen
AgeCommit message (Collapse)AuthorFilesLines
2023-02-20[llvm][Uniformity] A phi with an undef argument is not always divergentSameer Sahasrabuddhe1-1/+1
The uniformity analysis treated an undef argument to phi to be distinct from any other argument, equivalent to calling PHINode::hasConstantValue() instead of PHINode::hasConstantOrUndefValue(). Such a phi was reported as divergent. This is different from the older divergence analysis which treats such a phi as uniform. Fixed uniformity analysis to match the older behaviour. The original behaviour was added to DivergenceAnalysis in D19013. But it is not clear if relying on the undef value is safe. The defined values are not constant per se; they just happen to be uniform and the non-constant uniform value may not dominate the PHI. Reviewed By: ruiling Differential Revision: https://reviews.llvm.org/D144254
2023-02-19Use APInt::getSignificantBits instead of APInt::getMinSignedBits (NFC)Kazu Hirata4-10/+9
Note that getMinSignedBits has been soft-deprecated in favor of getSignificantBits.
2023-02-19[llvm] Use APInt::isAllOnes instead of isAllOnesValue (NFC)Kazu Hirata1-2/+2
Note that isAllOnesValue has been soft-deprecated in favor of isAllOnes.
2023-02-19Use APInt::isOne instead of APInt::isOneValue (NFC)Kazu Hirata2-2/+2
Note that isOneValue has been soft-deprecated in favor of isOne.
2023-02-19Use APInt::getAllOnes instead of APInt::getAllOnesValue (NFC)Kazu Hirata2-2/+2
Note that getAllOnesValue has been soft-deprecated in favor of getAllOnes.
2023-02-19[llvm] Use APInt::getZero instead of APInt::getNullValue (NFC)Kazu Hirata2-7/+7
Note that APInt::getNullValue has been soft-deprecated in favor of APInt::getZero.
2023-02-19Use APInt::isZero instead of APInt::isNulLValue (NFC)Kazu Hirata1-6/+3
Note that APInt::isNullValue has been soft-deprecated in favor of APInt::isZero.
2023-02-19Use APInt::count{l,r}_{zero,one} (NFC)Kazu Hirata7-57/+56
2023-02-19[GlobalISel] Fix a store-merging bug due to use of >= instead of >.Amara Emerson1-10/+11
This fixes a corner case where we would skip doing an alias check because of a >= vs > bug, due to the presence of a non-aliasing instruction, in this case the load %safeld. Fixes issue #59376
2023-02-19Use APInt::popcount instead of APInt::countPopulation (NFC)Kazu Hirata2-5/+5
This is for consistency with the C++20-style bit manipulation functions in <bit>.
2023-02-18[GlobalISel] Fix G_ZEXTLOAD being converted to G_SEXTLOAD incorrectly.Amara Emerson1-4/+7
The extending loads combine tries to prefer sign-extends folding into loads vs zexts, and in cases where a G_ZEXTLOAD is first used by a G_ZEXT, and then used by a G_SEXT, it would select the G_SEXT even though the load is already zero-extending. Fixes issue #59630
2023-02-17[WebAssembly] Initial support for reference type externref in clangPaulo Matos1-6/+2
This patch introduces a new type __externref_t that denotes a WebAssembly opaque reference type. It also implements builtin __builtin_wasm_ref_null_extern(), that returns a null value of __externref_t. This lays the ground work for further builtins and reference types. Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D122215
2023-02-17[GlobalISel] Combine out-of-range shifts to undef.Amara Emerson1-0/+10
Differential Revision: https://reviews.llvm.org/D144303
2023-02-17[MachineCombiner] Support local strategy for tracesAnton Sidorenko2-5/+15
For in-order cores MachineCombiner makes better decisions when the critical path is calculated only for the current basic block and does not take into account other blocks from the trace. This patch adds a virtual method to TargetInstrInfo to allow each target decide which strategy to use. Depends on D140541 Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D140542
2023-02-17[DAGCombiner] Teach MatchContextClass classes to use ↵Yeting Kuo1-7/+21
TargetLowering::isOperationLegalOrCustom(). Some of TargetLowering functions needed opcodes are often used in DAGCombiner. The patch make those MatchContextClass classes have TargetLowering members and pass specific opcodes for those TargetLowering functions. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D144075
2023-02-16[CodeGen] Fix warningsKazu Hirata1-4/+5
This patch fixes: llvm/lib/CodeGen/CallBrPrepare.cpp:154:14: error: unused variable 'IsDominated' [-Werror,-Wunused-variable] llvm/lib/CodeGen/CallBrPrepare.cpp:150:13: error: unused function 'PrintDebugDomInfo' [-Werror,-Wunused-function]
2023-02-16[llvm] add CallBrPrepare pass to pipelinesNick Desaulniers2-3/+6
Capstone of https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8 Clang changes are still necessary to enable the use of outputs along indirect edges of asm goto statements. Link: https://github.com/llvm/llvm-project/issues/53562 Reviewed By: void Differential Revision: https://reviews.llvm.org/D140180
2023-02-16[llvm][SelectionDAGBuilder] codegen callbr.landingpad intrinsicNick Desaulniers2-1/+116
Given a CallBrInst, retain its first virtual register in SelectionDagBuilder's FunctionLoweringInfo if there's corresponding landingpad. Walk the list of COPY MachineInstr to find the original virtual and physical registers defined by the INLINEASM_BR MachineInst. Test cases from https://reviews.llvm.org/D139565. Link: https://github.com/llvm/llvm-project/issues/59538 Part 3 from https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8 Follow up patches still need to wire up CallBrPrepare into the pass pipelines. Reviewed By: efriedma, void Differential Revision: https://reviews.llvm.org/D140160
2023-02-16[llvm][CallBrPrepare] use SSAUpdater to use intrinsic valueNick Desaulniers1-4/+76
Now that we've inserted a call to an intrinsic, we need to update certain previous uses of CallBrInst values to use the value of this intrinsic instead. There are 3 cases to handle: 1. The @llvm.callbr.landingpad.<type>() intrinsic call is in the same BasicBlock as the use of the callbr we're replacing. 2. The use is dominated by the direct destination. 3. The use is not dominated by the direct destination, and may or may not be dominated by the indirect destination. Part 2c of https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8. Reviewed By: efriedma, void, jyknight Differential Revision: https://reviews.llvm.org/D139970
2023-02-16[llvm][CallBrPrepare] add llvm.callbr.landingpad intrinsicNick Desaulniers1-0/+24
Insert a new intrinsic call after splitting critical edges, and verify it. Later commits will update the SSA values to use this new value along indirect branches rather than the callbr's value, and have SelectionDAG consume this new value. Part 2b of https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8. Reviewed By: efriedma, jyknight Differential Revision: https://reviews.llvm.org/D139883
2023-02-16[llvm][CallBrPrepare] split critical edgesNick Desaulniers1-10/+69
If we have a CallBrInst with output that's used, we need to split critical edges so that we have some place to insert COPYs for physregs to virtregs. Part 2a of https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8. Test cases and logic re-purposed from D138078. Reviewed By: efriedma, void, jyknight Differential Revision: https://reviews.llvm.org/D139872
2023-02-16[llvm] boilerplate for new callbrprepare codegen IR passNick Desaulniers4-0/+79
Because this pass is to be a codegen pass, it must use the legacy pass manager. Link: https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8 Reviewed By: aeubanks, void Differential Revision: https://reviews.llvm.org/D139861
2023-02-16[MachineCombiner][NFC] Rename `MinInstr` to `TraceEnsemble`Anton Sidorenko1-22/+21
We are about to allow different trace strategies for MachineCombiner. Make the name of the ensemble strategy-neutral. Depends on D140540 Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D140541
2023-02-15Use llvm::has_single_bit<uint32_t> (NFC)Kazu Hirata6-10/+14
This patch replaces isPowerOf2_32 with llvm::has_single_bit<uint32_t> where the argument is wider than uint32_t.
2023-02-15[MachineTraceMetrics] Add local strategyAnton Sidorenko1-0/+17
This strategy makes each trace local to the basic block. For in-order cores some heuristics work better when we do local decisions. For example, MachineCombiner may expect that instructions outside the current basic block do not lengthen the critical path when we execute instructions in order or the core has a small re-order buffer. This patch only introduce the strategy, real use-case is added in the further pathes. Depends on D140539 Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D140540
2023-02-15[DAGCombine] Fold redundant selectSamuel Parker1-0/+61
Recommit bbdf24357932b064f2aa18ea1356b474e0220dde. Original commit message: If a chain of two selects share a true/false value and are controlled by two setcc nodes, that are never both true, we can fold away one of the selects. So, the following: (select (setcc X, const0, eq), Y, (select (setcc X, const1, eq), Z, Y)) Can be combined to: select (setcc X, const1, eq) Z, Y Differential Revision: https://reviews.llvm.org/D142535
2023-02-14Add transform (and/or (icmp eq/ne (A, C)), (icmp eq/ne (A, -C))) -> (icmp ↵Noah Goldstein1-23/+46
eq/ne (ABS A), ABS(C)) This can be beneficial if there is a fast `ABS` (For example with X86 `vpabs`) or if there is a dominating ABS(A) in the `DAG`. Note `C` is constant so `ABS(C)` is just a constant. Alive2 Links: EQ: https://alive2.llvm.org/ce/z/829F-c NE: https://alive2.llvm.org/ce/z/tsS8bU Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D142601
2023-02-14Add Transform for `(and/or (eq/ne A,Pow2),(eq/ne A,-Pow2))`->`(eq/ne (and ↵Noah Goldstein1-0/+65
(and A,Pow2),~(Pow2*2)), 0)` In many instances this can be preferable if the `icmp` -> `i1` cannot be done in one instruction (such as X86 for scalars). At the moment guarded behind `TLI.isDesirableToCombineLogicOpOfSETCC`. alive2 links: https://alive2.llvm.org/ce/z/nLm5sN https://alive2.llvm.org/ce/z/moEcyE Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D142344
2023-02-14Revert "[CGP] Add generic TargetLowering::shouldAlignPointerArgs() ↵Jake Egan2-39/+2
implementation" These commits are causing a test-suite build failure on AIX. Revert for now for time to investigate. https://lab.llvm.org/buildbot/#/builders/214/builds/5779/steps/9/logs/stdio This reverts commit bd87a2449da0c82e63cebdf9c131c54a5472e3a7 and 4c72266830ffa332ebb7cf1d3bbd6c56d001fa0f.
2023-02-14[CodeGen] Trivial simplification of some getRegisterType calls. NFC.Jay Foad2-2/+2
2023-02-14DAG: Remove hasBitPreservingFPLogicMatt Arsenault1-5/+12
This doesn't make sense as an option. fneg and fabs are bit preserving by definition. If a target has some fneg or fabs instruction that are not bitpreserving it's incorrect to lower fneg/fabs to use it.
2023-02-14[MachineTraceMetrics][NFC] Move Strategy enum out of the classAnton Sidorenko3-6/+8
Make forward declaration possible to reduce amount of dependencies and reduce re-compilation burden caused by further patches. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D140539
2023-02-14DAG: Relax foldBitcastedFPLogic conditionsMatt Arsenault1-3/+13
Requiring a bitcast to exist was unhelpful. The most basic cases are always going to be a CopyFromReg or load, so they would need a new cast inserted. Don't require a bitcast if it's a free operation. I don't think this logic makes particularly much sense (it seems to be imparting special interpretation of bitcast), but this needs to be in sync with foldSignChangeInBitcast. We should also get rid of this hasBitPreservingFPLogic hook. fabs/fneg are bitpreserving or incorrectly implemented, so this should just be a regular legality check.
2023-02-14Use llvm::bit_cast (NFC)Kazu Hirata2-5/+5
2023-02-14Move global namespace cl::opt inside llvm::Fangrui Song4-5/+6
2023-02-14[DAG] Handle build_vector with all undefs in reduceBuildVecTruncToBitCastpvanhout1-1/+1
While working on D143731 I hit a case where a build_vector with 2 undef operands could be generated (with one undef hidden behind a bitcast). That made `reduceBuildVecTruncToBitCast` crash because it seems to assume there is at least one good operand. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D143886
2023-02-13Revert "[DAGCombiner] handle more store value forwarding"Arthur Eubanks1-48/+11
This reverts commit f35a09daebd0a90daa536432e62a2476f708150d. Causes miscompiles, see D138899
2023-02-13Revert "[DAGCombiner] fix comments for D138899; NFC"Arthur Eubanks1-12/+8
This reverts commit 63854f91d3ee1056796a5ef27753648396cac6ec. Dependent commit to be reverted.
2023-02-14[PowerPC][GISel] add support for fpconstantChen Zheng3-0/+45
Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D133340
2023-02-13[DAGCombine] Allow DAGCombine to remove dead masked stores.Dinar Temirbulatov1-0/+17
Remove a dead masked store if another one has the same base pointer and mask or the following store has all true constant mask and size if equal or bigger to the first store. Differential Revision: https://reviews.llvm.org/D143069
2023-02-13[HardwareLoops] NewPM support.Samuel Parker2-55/+118
With the NPM, we're now defaulting to preserving LCSSA, so a couple of tests have changed slightly. Differential Revision: https://reviews.llvm.org/D140982
2023-02-11[DFAPacketizer] Move DefaultVLIWScheduler class declaration to header fileDarshan Bhat1-30/+0
This change moves "DefaultVLIWScheduler" class declaration from DFAPacketizer.cpp to DFAPacketizer.h. This is needed because there is a protected class member of type "DefaultVLIWScheduler*" in "VLIWPacketizerList" class. The derived classes cannot use this memeber unless declaration is available to it. More specifically : // Without this change ``` class HexagonPacketizerList : public VLIWPacketizerList { public : HexagonPacketizerList() { // Below line will cause incomplete class error since // declaration was not available through header. VLIWScheduler->schedule(); } } ``` Reviewed By: kparzysz Differential Revision: https://reviews.llvm.org/D139767
2023-02-10[DebugInfo] Handle missed DW_FORM_addrx3 and DW_FORM_strx3 casesBenjamin Maxwell1-0/+1
This fixes a few places where the addrx3 and strx3 forms were missed. Previously this meant if one of these forms appeared somewhere various errors could occur. This now also adds an extra test case for the addrx3 form (which previously failed). Differential Revision: https://reviews.llvm.org/D143488
2023-02-10[Assignment Tracking] Fix fragment index error in getDerefOffsetInBytesOCHyams1-8/+10
Without this patch `getDerefOffsetInBytes` incorrectly always returns `std::nullopt` for expressions with fragments due to an off-by-one error with fragment element indices. Reviewed By: StephenTozer Differential Revision: https://reviews.llvm.org/D143567
2023-02-10[NFC][TargetParser] Replace uses of llvm/Support/Host.hArchibald Elliott1-1/+1
The forwarding header is left in place because of its use in `polly/lib/External/isl/interface/extract_interface.cc`, but I have added a GCC warning about the fact it is deprecated, because it is used in `isl` from where it is included by Polly.
2023-02-10[AMDGPU] Run unmerge combines post regbankselectPierre van Houtryve1-0/+9
RegBankSelect can insert G_UNMERGE_VALUES in a lot of places which left us with a lot of unmerge/merge pairs that could be simplified. These often got in the way of pattern matching and made codegen worse. This patch: - Makes the necessary changes to the merge/unmerge combines so they can run post RegBankSelect - Adds relevant unmerge combines to the list of RegBankSelect combines for AMDGPU - Updates some tablegen patterns that were missing explicit cross-regbank copies (V_BFI patterns were causing constant bus violations with this change). This seems to be mostly beneficial for code quality. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D142192
2023-02-10[llvm][DebugInfo] Add DW_TAG_imported_declaration to accelerator tablesMichael Buch1-1/+9
**Summary** After this patch, `DW_TAG_imported_declaration`s will be emitted into the DWARF accelerator tables (under `.apple_namespaces`) **Motivation** Currently LLDB expression evaluation doesn't see through namespace aliases. This is because LLDB only considers namespaces that are part of `.apple_namespaces` when building a nested namespace identifier for C++, which currently doesn't include import declarations. The alternative to putting imports into accelerator tables is to do a linear scan of a `DW_TAG_namespace` and look for import declarations that look like they would satisfy the lookup request, which is prohibitively expensive. **Testing** * Added unit-test Differential Revision: https://reviews.llvm.org/D143397
2023-02-09[MachineOutliner] Make getOutliningType partially target-independentduk1-0/+66
The motivation behind this patch is to unify some of the outliner logic across architectures. This looks nicer in general and makes fixing [issues like this](https://reviews.llvm.org/D124707#3483805) easier. There are some notable changes here: 1. `isMetaInstruction()` is used directly instead of checking for specific meta-instructions like `IMPLICIT_DEF` or `KILL`. This was already done in the RISC-V implementation, but other architectures still did hardcoded checks. - As an exception to this, CFI instructions are explicitly delegated to the target because RISC-V has different handling for those. 2. `isTargetIndex()` checks are replaced with an assert; none of the architectures supported actually use `MO_TargetIndex` at this point in time. 3. `isCFIIndex()` and `isFI()` checks are also replaced with asserts, since these operands should not exist in [any context](https://reviews.llvm.org/D122635#3447214) at this stage in the pipeline. Reviewed by: paquette Differential Revision: https://reviews.llvm.org/D125072
2023-02-09Revert "HHVM calling conventions."Amir Aupov2-32/+16
This reverts commit cce239c45d6ef3865a017b5b3f935964e0348734. HHVM calling conventions are unused. Remove them by partially reverting the commit. Reviewed By: MaskRay, MatzeB Differential Revision: https://reviews.llvm.org/D124330
2023-02-09[SelectionDAG] Do not second-guess alignment for allocaAndrew Savonichev1-14/+1
Alignment of an alloca in IR can be lower than the preferred alignment on purpose, but this override essentially treats the preferred alignment as the minimum alignment. The patch changes this behavior to always use the specified alignment. If alignment is not set explicitly in LLVM IR, it is set to DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign. Tests are changed as well: explicit alignment is increased to match the preferred alignment if it changes output, or omitted when it is hard to determine the right value (e.g. for pointers, some structs, or weird types). Differential Revision: https://reviews.llvm.org/D135462
generated by cgit v1.1 at 2025-09-30 00:16:07 +0000