riscv-gnu-toolchain/llvm.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2025-12-01	[SPIRV] Add legalization for long vectors (#169665)	Steven Perron	1	-0/+20
2025-12-01	[LLVM][CodeGen] Remove failure cases when widening EXTRACT/INSERT_SUBVECTOR. ...	Paul Walker	2	-19/+79
2025-12-01	[SelectionDAG] Add SelectionDAG::getTypeSize. NFC (#169764)	Luke Lau	4	-61/+39
2025-11-30	[DAG] getCarry - always succeed if we encounter a i1 type during trunc/ext pe...	Simon Pilgrim	1	-3/+3
2025-11-29	Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)	theRonShark	3	-58/+7
2025-11-29	[RegAlloc] Relax the split constrain on MBB prolog (#168259)	Luo Yuanke	3	-7/+58
2025-11-28	[AArch64][SVE] Add basic support for `@llvm.masked.compressstore` (#168350)	Benjamin Maxwell	1	-12/+15
2025-11-27	Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminat...	Alex Bradbury	1	-5/+7
2025-11-27	[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no...	Nathan Corbyn	1	-7/+5
2025-11-26	Add IR and codegen support for deactivation symbols.	Peter Collingbourne	13	-29/+130
2025-11-26	CodeGen: Remove PointerLikeRegClass handling from codegen (#159883)	Matt Arsenault	1	-4/+0
2025-11-26	[dwarf] make dwarf fission compatible with RISCV relaxations 2/2 (#164813)	daniilavdeev	1	-3/+5
2025-11-26	[dwarf] make dwarf fission compatible with RISCV relaxations 1/2 (#166597)	daniilavdeev	1	-25/+39
2025-11-25	CodeGen: Move libcall lowering configuration to subtarget (#168621)	Matt Arsenault	2	-2/+6
2025-11-25	[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)	Drew Kersnar	2	-5/+7
2025-11-25	Revert "Reland "RegisterCoalescer: Add implicit-def of super register when co...	Sander de Smalen	2	-172/+15
2025-11-24	Reland "RegisterCoalescer: Add implicit-def of super register when coalescing...	Sander de Smalen	2	-15/+172
2025-11-24	Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...	hstk30-hw	1	-1/+1
2025-11-23	Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...	Aiden Grossman	1	-1/+1
2025-11-23	[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)	hstk30-hw	1	-1/+1
2025-11-22	[llvm] Use llvm::equal (NFC) (#169173)	Kazu Hirata	1	-2/+1
2025-11-22	[CallBrPrepare] Prefer Function &F over Function &Fn	Aiden Grossman	1	-10/+10
2025-11-22	[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit trunc...	Hongyu Chen	1	-0/+4
2025-11-20	TargetLowering: Avoid hardcoding OpenBSD + __guard_local name (#167744)	Matt Arsenault	1	-10/+12
2025-11-20	[DAGCombiner] Remove unneeded m_BitReverse from visitBITREVERSE. NFC (#168918)	Craig Topper	1	-2/+2
2025-11-20	Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#...	Matt Arsenault	1	-6/+10
2025-11-20	[SDAG] Fix whitespace errors (NFC) (#168897)	Ramkumar Ramachandra	2	-17/+17
2025-11-20	[DebugInfo] Force early line-zero calls to have meaningful locations (#156850)	Jeremy Morse	1	-0/+26
2025-11-19	[CFIInserter] Turn a reachable llvm_unreachable into a report_fatal_error. (#...	Craig Topper	1	-1/+2
2025-11-20	DAG: Fix constructing a temporary TargetTransformInfo instance (#168480)	Matt Arsenault	3	-21/+14
2025-11-20	RenameIndependentSubregs: try to only implicit def used subregs (#167486)	Carl Ritson	1	-7/+26
2025-11-19	DAG: Use poison for some vector result widening (#168290)	Matt Arsenault	1	-12/+12
2025-11-19	CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)	Matt Arsenault	2	-3/+5
2025-11-19	DAG: Use poison when splitting vector_shuffle results (#168176)	Matt Arsenault	1	-1/+1
2025-11-19	[AArch64][GlobalISel] Check unmergeSrc is a vector in matchCombineBuildUnmerg...	Ryan Cowan	1	-0/+3
2025-11-19	[DAG] Update canCreateUndefOrPoison to handle ISD::VECTOR_COMPRESS (#168010)	陈子昂	1	-0/+3
2025-11-18	Introduce DwarfUnit::addBlock helper method (#168446)	Tom Tromey	2	-65/+24
2025-11-18	[GISel] Use getScalarSizeInBits in LegalizerHelper::lowerBitCount (#168584)	Craig Topper	1	-3/+3
2025-11-18	[RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745)	Craig Topper	1	-2/+9
2025-11-18	[GISel][RISCV] Compute CTPOP of small odd-sized integer correctly (#168559)	Hongyu Chen	1	-0/+4
2025-11-18	[AArch64][GISel] Don't crash in known-bits when copying from vectors to non-v...	Nathan Corbyn	1	-2/+9
2025-11-18	[CGP]: Optimize mul.overflow. (#148343)	Hassnaa Hamdi	1	-0/+182
2025-11-18	[AArch64][GlobalISel] Add better basic legalization for llround. (#168427)	David Green	1	-0/+12
2025-11-18	[DAGCombiner] Fold select into partial.reduce.add operands. (#167857)	Sander de Smalen	2	-14/+59
2025-11-17	[MLGO] Fully Remove MLRegalloc Experimental Features (#168252)	Aiden Grossman	1	-137/+0
2025-11-17	[AArch64][GlobalISel] Add combine for build_vector(unmerge, unmerge, undef, u...	Ryan Cowan	1	-1/+83
2025-11-17	[DAG] Add strictfp implicit def reg after metadata. (#168282)	David Green	2	-14/+14
2025-11-17	[MachinePipeliner] Detect a cycle in PHI dependencies early on (#167095)	Abinaya Saravanan	1	-0/+60
2025-11-17	[InlineAsmLowering] unsigned -> TypeSize for getTypeStoreSize result	pvanhout	1	-1/+1
2025-11-17	[GlobalMerge]Prefer use global-merge-max-offset instead of the target-specifi...	hstk30-hw	1	-1/+4