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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-07-02[SDAG] Prefer scalar for prefix of vector GEP expansion (#146719)Philip Reames1-14/+19
2025-06-24DAG: Move get_dynamic_area_offset type check to IR verifier (#145268)Matt Arsenault1-6/+0
2025-06-18[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel (#...Orlando Cazalet-Hyams1-63/+0
2025-06-17[DebugInfo][RemoveDIs] Remove a swathe of debug-intrinsic code (#144389)Jeremy Morse1-4/+1
2025-06-17[LLVM][CodeGen] Lower ConstantInt vectors like shufflevector base splats. (#1...Paul Walker1-2/+20
2025-06-12[CodeGen] Inline stack guard check on Windows (#136290)Omair Javaid1-17/+78
2025-06-09[SelectionDAG][X86] Handle `llvm.type.test` in DAGBuilder (#142939)Abhishek Kaushik1-0/+5
2025-06-04[SelectionDAG] Use reportFatalUsageError() for invalid operand bundles (#142613)Nikita Popov1-15/+17
2025-06-03[ARM,AArch64] Don't put BTI at asm goto branch targets (#141562)Simon Tatham1-1/+5
2025-05-30[SDAG] Remove noundef workaround for range metadata/attributes (#141745)Nikita Popov1-13/+3
2025-05-28[SelectionDAG] Introduce ISD::PTRADD (#140017)Fabian Ritter1-10/+8
2025-05-26[IR] Add llvm.vector.[de]interleave{4,6,8} (#139893)Luke Lau1-0/+18
2025-05-22[CodeGen] Add SSID & Atomic Ordering to IntrinsicInfo (#140896)Pierre van Houtryve1-3/+10
2025-05-19[AMDGPU] Set AS8 address width to 48 bitsAlexander Richardson1-3/+12
2025-05-15[SelectionDAG] Add an ISD node for for get.active.lane.mask (#139084)Kerry McLaughlin1-2/+3
2025-05-15CodeGen: Add ISD::AssertNoFPClass (#138839)YunQiang Su1-3/+12
2025-05-10[IR] Teach getAsmString to return StringRef (NFC) (#139406)Kazu Hirata1-1/+1
2025-05-06[IR] Remove the AtomicMem*Inst helper classes (#138710)Philip Reames1-3/+3
2025-05-06[SDAG] Merge memcpy and memcpy.inline lowering paths (#138619)Philip Reames1-24/+6
2025-05-05[IntrinsicInst] Remove MemCpyInlineInst and MemSetInlineInst [nfc] (#138568)Philip Reames1-22/+8
2025-05-05[CodeGen] Use range-based for loops (NFC) (#138488)Kazu Hirata1-2/+2
2025-05-04Revert "[CodeGen] Use range-based for loops (NFC) (#138434)"Nico Weber1-2/+2
2025-05-04[CodeGen] Use range-based for loops (NFC) (#138434)Kazu Hirata1-2/+2
2025-04-30Reland [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instruction...Jonathan Thackray1-0/+6
2025-04-30Revert "CodeGen: Add ISD::AssertNoFPClass (#135946)"YunQiang Su1-12/+3
2025-04-28Revert "[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructio...Jonathan Thackray1-6/+0
2025-04-28[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#136...Jonathan Thackray1-0/+6
2025-04-25CodeGen: Add ISD::AssertNoFPClass (#135946)YunQiang Su1-3/+12
2025-04-24[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic...Craig Topper1-1/+2
2025-04-22[SelectionDAG] Pass LoadExtType when ATOMIC_LOAD is created. (#136653)Craig Topper1-2/+2
2025-04-18[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)Philip Reames1-3/+3
2025-04-10Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the ...zhijian lin1-1/+1
2025-04-09Revert "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the ...Jakub Kuderski1-1/+1
2025-04-07[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison v...zhijian lin1-1/+1
2025-03-27[CodeGen] Simplify code using TypeSize overloads of getMachineMemOperand [nfc]Philip Reames1-14/+10
2025-03-21[llvm:ir] Add support for constant data exceeding 4GiB (#126481)pzzp1-1/+1
2025-03-20[SelectionDAG] Not issue TRAP node if naked function (#132147)yonghong-song1-11/+2
2025-03-20[X86][NFCI] Add IsStore parameter to hasConditionalLoadStoreForType (#132153)Phoebe Wang1-4/+4
2025-03-20[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)Diana Picus1-4/+9
2025-03-10[WebAssembly] Remove wasm-specific findWasmUnwindDestinations (#130374)Heejin Ahn1-61/+5
2025-03-08DAG: Use phi in alloca constant case to create virtual registers (#130254)Matt Arsenault1-1/+1
2025-03-07[win] Fix EH Cont Guard targets when SEH personality is used (#129612)Daniel Paoliello1-3/+9
2025-03-06[win] NFC: Rename `EHCatchret` to `EHCont` to allow for EH Continuation targe...Daniel Paoliello1-2/+2
2025-03-04DAG: Use phi to create vregs instead of the constant input (#129464)Matt Arsenault1-1/+1
2025-03-03[SelectionDAG] Use `poison` instead of `undef` for `dbg.values` (#127915)Pedro Lobo1-12/+12
2025-03-02[SelectionDAG] Use Register and MCRegister. NFCCraig Topper1-16/+13
2025-02-25[WebAssembly] Make llvm.wasm.throw invokable (#128104)Heejin Ahn1-7/+19
2025-02-20Revert "[CodeGen] Remove static member function Register::isVirtualRegister. ...Christopher Di Bella1-2/+3
2025-02-20Revert "[CodeGen] Remove static member function Register::isPhysicalRegister....Christopher Di Bella1-3/+4
2025-02-20[CodeGen] Remove static member function Register::isPhysicalRegister. NFCCraig Topper1-4/+3
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