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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
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2013-02-16Use const reference instead of vector object when passing an argument toJakub Staszak1-1/+1
updateScheduledPressure method. llvm-svn: 175362
2013-02-13MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick1-1/+6
llvm-svn: 175067
2013-01-29MIsched: cleanup code. Use isBoundaryNode().Andrew Trick1-2/+4
llvm-svn: 173775
2013-01-25Use const reference instead of vector copying.Jakub Staszak1-1/+2
llvm-svn: 173497
2013-01-25MIsched: Print block name. No functionality.Andrew Trick1-1/+2
llvm-svn: 173433
2013-01-25MachineScheduler support for viewGraph.Andrew Trick1-1/+88
llvm-svn: 173432
2013-01-25MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick1-29/+33
Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
2013-01-25MISched: Add SchedDFSResult to ScheduleDAGMI to formalize theAndrew Trick1-25/+55
interface and allow other strategies to select it. llvm-svn: 173413
2013-01-24MachineScheduler: enable biasCriticalPath for all DAGs.Andrew Trick1-0/+4
llvm-svn: 173318
2013-01-11Follow-up typo correction from building the wrong branch.Andrew Trick1-2/+2
llvm-svn: 172224
2013-01-11Fix typo from r170452. Affects -enable-misched heuristics.Andrew Trick1-2/+2
llvm-svn: 172223
2013-01-09MIsched: add an ILP window property to machine model.Andrew Trick1-10/+2
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
2012-12-18MISched: Cleanup, redundant statement.Andrew Trick1-1/+0
llvm-svn: 170453
2012-12-18MISched: Heuristics, compare latency more precisely. It matters more for ↵Andrew Trick1-43/+38
some targets. llvm-svn: 170452
2012-12-18MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to ↵Andrew Trick1-3/+0
compute it. llvm-svn: 170451
2012-12-18MISched: cleanup, use the proper iterator type.Andrew Trick1-1/+1
llvm-svn: 170450
2012-12-18MISched: minor improvement, initialize remaining resources before the first ↵Andrew Trick1-0/+10
scheduling decision. llvm-svn: 170449
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth1-5/+4
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-01misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick1-0/+4
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. llvm-svn: 169072
2012-12-01misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick1-0/+2
assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. llvm-svn: 169069
2012-11-29misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer1-0/+2
This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. llvm-svn: 168885
2012-11-28misched: Analysis that partitions the DAG into subtrees.Andrew Trick1-15/+56
This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
2012-11-28misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick1-1/+1
llvm-svn: 168772
2012-11-28misched: Debug output fix. Use an always valid iterator.Andrew Trick1-1/+1
llvm-svn: 168767
2012-11-13misched: Allow subtargets to enable misched and dependent options.Andrew Trick1-2/+2
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
2012-11-12misched: rename interfaceto avoid gcc warningsAndrew Trick1-2/+1
llvm-svn: 167753
2012-11-12misched: Target-independent support for MacroFusion.Andrew Trick1-5/+61
Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. llvm-svn: 167744
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick1-12/+176
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick1-8/+18
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
2012-11-09Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer1-0/+1
llvm-svn: 167618
2012-11-07misched: Heuristics based on the machine model.Andrew Trick1-146/+762
misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. llvm-svn: 167527
2012-11-06misched: Rename RemainingCount to avoid confusion with remaining resources.Andrew Trick1-6/+6
llvm-svn: 167443
2012-10-16misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick1-1/+1
allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. llvm-svn: 166001
2012-10-15misched: ILP scheduler for experimental heuristics.Andrew Trick1-20/+104
llvm-svn: 165950
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick1-10/+20
Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
2012-10-08misched: avoid scheduling an instruction twice.Andrew Trick1-25/+29
llvm-svn: 165416
2012-09-14misched: add a hook for custom DAG postprocessing.Andrew Trick1-0/+9
llvm-svn: 163915
2012-09-11Release build: guard dump functions withManman Ren1-1/+1
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
2012-09-11Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick1-256/+100
The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren1-0/+2
No functional change. llvm-svn: 163339
2012-08-23Simplify the computeOperandLatency API.Andrew Trick1-10/+8
The logic for recomputing latency based on a ScheduleDAG edge was shady. This bypasses the problem by requiring the client to provide operand indices. This ensures consistent use of the machine model's API. llvm-svn: 162420
2012-08-22Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper1-1/+1
did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
2012-07-23Fix a typo (the the => the)Sylvestre Ledru1-1/+1
llvm-svn: 160621
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick1-1/+2
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-02misched: allow NULL InstrItineraries.Andrew Trick1-0/+1
llvm-svn: 159599
2012-06-29misched: avoid scheduling instructions that can't be dispatched.Andrew Trick1-6/+29
llvm-svn: 159408
2012-06-29misched: count micro-ops toward the issue limit.Andrew Trick1-10/+19
llvm-svn: 159407
2012-06-16Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer1-1/+7
llvm-svn: 158608
2012-06-06Move RegisterClassInfo.h.Andrew Trick1-1/+1
Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
2012-06-06Move RegisterPressure.h.Andrew Trick1-1/+1
Make it a general utility for use by Targets. llvm-svn: 158097
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