riscv-gnu-toolchain/llvm.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2009-06-15	Part 1.	Evan Cheng	1	-1/+1
	- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed before register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
2009-06-14	Move register allocation preference (or hint) from LiveInterval to ↵	Evan Cheng	1	-0/+2
	MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
2009-04-15	Move MachineRegisterInfo::setRegClass out of line.	Dan Gohman	1	-0/+20
	llvm-svn: 69126
2008-12-08	Move createVirtualRegister out-of-line.	Dan Gohman	1	-0/+18
	llvm-svn: 60684
2008-10-20	Add a register class -> virtual registers map.	Evan Cheng	1	-0/+1
	llvm-svn: 57844
2008-07-07	Assert that all MachineInstrs update PhysRegUseDefLists in	Dan Gohman	1	-0/+3
	their cleanup code. llvm-svn: 53194
2008-02-13	Added debugging routine dumpUses.	Evan Cheng	1	-0/+8
	llvm-svn: 47042
2008-02-10	Rename MRegisterInfo to TargetRegisterInfo.	Dan Gohman	1	-5/+5
	llvm-svn: 46930
2008-01-01	switch the register iterator to act more like hte LLVM value iterator: ↵	Chris Lattner	1	-2/+16
	dereferencing it now returns the machineinstr of the use. To get the operand, use I.getOperand(). Add a new MachineRegisterInfo::replaceRegWith, which is basically like Value::replaceAllUsesWith. llvm-svn: 45482
2008-01-01	Add a trivial but handy function to efficiently return the machine	Chris Lattner	1	-0/+15
	instruction that defines the specified vreg. Crazy. llvm-svn: 45480
2008-01-01	Implement automatically updated def/use lists for all MachineInstr register	Chris Lattner	1	-1/+27
	operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. llvm-svn: 45477
2007-12-31	Rename SSARegMap -> MachineRegisterInfo in keeping with the idea	Chris Lattner	1	-0/+20
	that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467