aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/MachineInstr.cpp
AgeCommit message (Collapse)AuthorFilesLines
2011-08-29Thumb2 parsing and encoding for IT blocks.Jim Grosbach1-0/+4
llvm-svn: 138773
2011-08-24Tidy up. Trailing whitespace.Jim Grosbach1-31/+31
llvm-svn: 138437
2011-08-19Don't treat a partial <def,undef> operand as a read.Jakob Stoklund Olesen1-1/+2
Normally, a partial register def is treated as reading the super-register unless it also defines the full register like this: %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def> This patch also uses the <undef> flag on partial defs to recognize non-reading operands: %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses would treat a coalesced copy as still reading the register, extending the live range artificially. My test case only works when I disable DCE so a dead copy is left for RegisterCoalescer, so I am not including it. <rdar://problem/9967101> llvm-svn: 138018
2011-08-04Print DBG_VALUE variable's location info as a comment.Devang Patel1-1/+13
llvm-svn: 136916
2011-07-07If known DebugLocs do not match then two DBG_VALUE machine instructions are ↵Devang Patel1-0/+5
not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". llvm-svn: 134620
2011-07-02Include a source location when complaining about bad inline assembly.Jakob Stoklund Olesen1-0/+24
Add a MI->emitError() method that the backend can use to report errors related to inline assembly. Call it from X86FloatingPoint.cpp when the constraints are wrong. This enables proper clang diagnostics from the backend: $ clang -c pr30848.c pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ ^ 1 error generated. llvm-svn: 134307
2011-07-01Take a stab at fixing the llvm-x86_64-linux-checks failure.Cameron Zwarich1-0/+2
llvm-svn: 134287
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng1-55/+55
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-27Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen1-1/+2
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. llvm-svn: 133902
2011-06-27Decode and pretty print inline asm operand descriptors.Jakob Stoklund Olesen1-1/+22
The INLINEASM MachineInstrs have an immediate operand describing each original inline asm operand. Decode the bits in MachineInstr::print() so it is easier to read: INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def> llvm-svn: 133901
2011-06-24Handle debug info for i128 constants.Devang Patel1-0/+3
llvm-svn: 133821
2011-05-12Re-commit 131172 with fix. MachineInstr identity checks should check deadEvan Cheng1-7/+23
markers. In some cases a register def is dead on one path, but not on another. This is passing Clang self-hosting. llvm-svn: 131214
2011-05-08Remove an assertion to fix PR9872.Jakob Stoklund Olesen1-1/+2
It can happen that a live debug variable is the last use of a sub-register, and the register allocator will pick a larger register class for the virtual register. If the allocated register doesn't support the sub-register index, just use %noreg for the debug variables instead of asserting. In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD register. The register is split and one part is inflated to GR32 and assigned %ESI because there are no more normal uses of sub_8bit_hi. Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will simply insert a %noreg instead, and the debug variable will be marked unavailable in that range. We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I don't know if DWARF even supports that. llvm-svn: 131073
2011-04-29Print out the 'nontemporal' info on a store.Bill Wendling1-0/+4
llvm-svn: 130562
2011-04-05Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen1-7/+2
addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. llvm-svn: 128888
2011-03-05Add FrameSetup MI flagsAnton Korobeynikov1-10/+23
llvm-svn: 127098
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen1-6/+4
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
2011-01-09Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen1-17/+4
without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. llvm-svn: 123107
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng1-8/+49
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
2011-01-07DBG_VALUE does not have any side effects; it also makes no sense to mark it ↵Evan Cheng1-1/+3
cheap as a copy. llvm-svn: 123031
2010-10-22Unbreak build.Evan Cheng1-0/+11
llvm-svn: 117155
2010-10-20Make CodeGen TBAA-aware.Dan Gohman1-3/+17
llvm-svn: 116890
2010-10-19Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.Jakob Stoklund Olesen1-3/+3
Pull an unsigned out of the Contents union such that it has the same size as two pointers and no padding. Arrange members such that the Contents union and all pointers can be 8-byte aligned without padding. This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be unaffected. llvm-svn: 116857
2010-09-21convert a couple more places to use the new getStore()Chris Lattner1-0/+4
llvm-svn: 114463
2010-09-21add some accessorsChris Lattner1-0/+7
llvm-svn: 114409
2010-09-21it's more elegant to put the "getConstantPool" andChris Lattner1-0/+12
"getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. llvm-svn: 114406
2010-09-21add some helpful accessors.Chris Lattner1-0/+8
llvm-svn: 114400
2010-09-21start pushing MachinePointerInfo out through the MachineMemOperand interfaceChris Lattner1-4/+5
to the MachineFunction construction methods. llvm-svn: 114390
2010-09-21refactor the Value*/offset pair from MachineMemOperand out to a newChris Lattner1-5/+5
MachinePointerInfo struct, no functionality change. This also adds an assert to MachineMemOperand::MachineMemOperand that verifies that the Value* is either null or is an IR pointer type. llvm-svn: 114389
2010-08-02Prefix `next' iterator operation with `llvm::'.Oscar Fuentes1-1/+1
Fixes potential ambiguity problems on VS 2010. Patch by nobled! llvm-svn: 110029
2010-07-28Print out the regclass of any virtual registers used by a machine instruction.Jakob Stoklund Olesen1-0/+31
llvm-svn: 109608
2010-07-04Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.Jakob Stoklund Olesen1-0/+2
llvm-svn: 107602
2010-07-02Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen1-7/+7
PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. llvm-svn: 107506
2010-06-29Print InlinedAt location.Devang Patel1-12/+23
llvm-svn: 107208
2010-06-18Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman1-0/+19
on calls and similar instructions. llvm-svn: 106353
2010-06-02Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen1-0/+23
instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
2010-06-01Properly compose subregister indices when coalescing.Jakob Stoklund Olesen1-1/+2
The comment about ordering of subreg indices is no longer true. This exposed a bug in the new substVirtReg method that is also fixed. llvm-svn: 105294
2010-05-28Add a TargetRegisterInfo::composeSubRegIndices hook with a defaultJakob Stoklund Olesen1-0/+19
implementation that is correct for most targets. Tablegen will override where needed. Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing subreg indices when sustituting registers. llvm-svn: 104985
2010-05-25Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen1-2/+6
llvm-svn: 104628
2010-05-21- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng1-9/+14
that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. llvm-svn: 104377
2010-05-21Add MachineInstr::readsWritesVirtualRegister() to determine if an instructionJakob Stoklund Olesen1-11/+15
reads or writes a register. This takes partial redefines and undef uses into account. Don't actually use it yet. That caused miscompiles. llvm-svn: 104372
2010-05-21Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen1-15/+11
register is read." This reverts r104322. I think it was causing miscompilations. llvm-svn: 104323
2010-05-21Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen1-11/+15
This correctly handles partial redefines and undef uses. llvm-svn: 104322
2010-05-21If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen1-5/+15
<imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. llvm-svn: 104320
2010-05-19Add MachineInstr::readsVirtualRegister() in preparation for proper handling ofJakob Stoklund Olesen1-1/+24
partial redefines. We are going to treat a partial redefine of a virtual register as a read-modify-write: %reg1024:6 = OP Unless the register is fully clobbered: %reg1024:6 = OP, %reg1024<imp-def> MachineInstr::readsVirtualRegister() knows the difference. The first case is a read, the second isn't. llvm-svn: 104149
2010-05-13Teach MachineLICM and MachineSink how to clear kill flags conservativelyDan Gohman1-0/+10
when they move instructions. llvm-svn: 103737
2010-04-28Pretty print DBG_VALUE machine instructions.Evan Cheng1-1/+9
Before: DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707 Now: DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707 llvm-svn: 102518
2010-04-09Use getNumImplicitDefs() and getNumImplicitUses().Bob Wilson1-24/+6
llvm-svn: 100850
2010-04-09Fix up some comments.Bob Wilson1-5/+3
llvm-svn: 100849
2010-04-08Coalescer should not delete copy instructions whose defs are partially dead. ↵Evan Cheng1-0/+13
e.g. %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> llvm-svn: 100804
generated by cgit v1.1 at 2025-10-23 16:47:15 +0000