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path: root/llvm/lib/CodeGen/MachineInstr.cpp
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2010-01-16Replace DebugLocTuple with DILocation.Devang Patel1-5/+5
llvm-svn: 93630
2010-01-13Further progration of metadata operands. TheDale Johannesen1-1/+7
dumper doesn't really do what I want yet, but at least it doesn't crash now. llvm-svn: 93272
2010-01-06Add <imp-def> and <imp-kill> operands when replacing virtual sub-register ↵Jakob Stoklund Olesen1-0/+9
defs and kills. An instruction like this: %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0 Must be replaced with this when substituting physical registers: %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def> llvm-svn: 92812
2010-01-04Change errs() to dbgs().David Greene1-1/+2
llvm-svn: 92545
2009-12-28snip one more #include from Metadata.hChris Lattner1-0/+1
llvm-svn: 92214
2009-12-25Remove dead store.Bill Wendling1-1/+1
llvm-svn: 92159
2009-12-25Remove dead store from copy-pasto.Bill Wendling1-1/+1
llvm-svn: 92158
2009-12-16Add @earlyclobber TableGen constraintJim Grosbach1-3/+21
llvm-svn: 91554
2009-12-07Follow up to 90488. Turn a check into an assertion.Evan Cheng1-2/+2
llvm-svn: 90815
2009-12-05Don't print the debug directory; it's often long and uninteresting. OmitDan Gohman1-2/+7
the column number if it is not known. Handle the case of a missing filename better. llvm-svn: 90630
2009-12-03Watch out for PHI instruction with no source operands.Evan Cheng1-0/+2
llvm-svn: 90488
2009-12-03Fill out codegen SSA updater. It's not yet tested.Evan Cheng1-0/+14
llvm-svn: 90395
2009-12-01Devang pointed out that this code should use DIScope instead ofDan Gohman1-3/+3
DICompileUnit. This code now prints debug filenames successfully. llvm-svn: 90181
2009-11-23Print the debug info line and column in MachineInstr::print even when there'sDan Gohman1-2/+3
no filename. This situation is apparently fairly common right now. llvm-svn: 89701
2009-11-16Initialize the new AsmPrinterFlags field to 0, fixing uses ofDan Gohman1-6/+8
uninitialized memory. llvm-svn: 88985
2009-11-09Print "..." instead of all the uninteresting register clobbers on callDan Gohman1-14/+54
instructions. This makes CodeGen dumps significantly less noisy. Example before: BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead> Same example after: BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ... llvm-svn: 86583
2009-11-06Use WriteAsOperand to print GlobalAddress MachineOperands. ThisDan Gohman1-1/+2
prints them with the leading '@'. llvm-svn: 86261
2009-10-31Make -print-machineinstrs more readable.Dan Gohman1-19/+28
- Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. llvm-svn: 85682
2009-10-30Initial target-independent CodeGen support for BlockAddresses.Dan Gohman1-0/+10
llvm-svn: 85556
2009-10-21Need a comma after imp-use.Evan Cheng1-1/+3
llvm-svn: 84749
2009-10-14Print earlyclobber for implicit-defs as well.Evan Cheng1-6/+6
llvm-svn: 84152
2009-10-13s/DebugLoc.CompileUnit/DebugLoc.Scope/gDevang Patel1-5/+6
s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g llvm-svn: 84054
2009-10-09Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman1-5/+7
is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
2009-10-09isTriviallyReMaterializable checks theDan Gohman1-2/+1
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do this check in its callers. llvm-svn: 83671
2009-10-07Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman1-1/+42
implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. llvm-svn: 83475
2009-10-05strength reduce a ton of type equality tests to check the typeid (ThroughChris Lattner1-1/+1
the new predicates I added) instead of going through a context and doing a pointer comparison. Besides being cheaper, this allows a smart compiler to turn the if sequence into a switch. llvm-svn: 83297
2009-09-29Remove std::string uses from DebugInfo interface.Devang Patel1-2/+1
llvm-svn: 83083
2009-09-25Move MachineMemOperand::getAlignment out of line, to avoid needingDan Gohman1-0/+6
MathExtras.h in MachineMemOperand.h. llvm-svn: 82822
2009-09-25Improve MachineMemOperand handling.Dan Gohman1-44/+63
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
2009-09-23Give MachineMemOperand an operator<<, factoring out code fromDan Gohman1-26/+42
two different places for printing MachineMemOperands. Drop the virtual from Value::dump and instead give Value a protected virtual hook that can be overridden by subclasses to implement custom printing. This lets printing be more consistent, and simplifies printing of PseudoSourceValue values. llvm-svn: 82599
2009-09-21Change MachineMemOperand's alignment value to be the alignment ofDan Gohman1-1/+1
the base pointer, without the offset. This matches MemSDNode's new alignment behavior, and holds more interesting information. llvm-svn: 82473
2009-09-17grammarJim Grosbach1-1/+1
llvm-svn: 82150
2009-08-23remove some uses of llvm/Support/Streams.hChris Lattner1-1/+0
llvm-svn: 79842
2009-08-23remove various std::ostream version of printing methods fromChris Lattner1-11/+1
MachineInstr and MachineOperand. This required eliminating a bunch of stuff that was using DOUT, I hope that bill doesn't mind me stealing his fun. ;-) llvm-svn: 79813
2009-08-13Push LLVMContexts through the IntegerType APIs.Owen Anderson1-1/+1
llvm-svn: 78948
2009-08-04Don't tamper with <undef> operands in MachineInstr::addRegisterKilled.Jakob Stoklund Olesen1-3/+1
For an undef operand, MO.getReg() is meaningless and we should not use it. Undef operands should be skipped entirely. llvm-svn: 78095
2009-08-03Fix Bug 4657: register scavenger asserts with subreg loweringJakob Stoklund Olesen1-0/+2
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG instriction because it is an identity copy, make sure that the same registers are alive before and after the elimination. When the super-register is marked <undef> this requires inserting an IMPLICIT_DEF instruction to make sure the super register is live. Fix a related bug where a kill flag on the inserted sub-register was not transferred properly. Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid. llvm-svn: 77989
2009-08-02Never add a kill flag to a constrained physical register in a two-addr ↵Jakob Stoklund Olesen1-0/+3
instruction. llvm-svn: 77906
2009-07-28Fix a typo.Evan Cheng1-1/+1
llvm-svn: 77369
2009-07-19Fix http://llvm.org/bugs/show_bug.cgi?id=4583Jakob Stoklund Olesen1-2/+6
Inline asm instructions may have additional <imp-def,kill> register operands. These operands are not marked with a flag like the normal asm operands, so we must not assert that there is a flag. llvm-svn: 76373
2009-07-16Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm ↵Jakob Stoklund Olesen1-8/+12
operands. The inline asm operands must be parsed from the first flag, you cannot assume that an immediate operand preceeding a register use operand is the flag. PowerPC "m" operands are represented as (flag, imm, reg) triples. isRegTiedToDefOperand() would incorrectly interpret the imm as the flag. llvm-svn: 76101
2009-07-14llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin1-2/+2
This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-11assert(0) -> LLVM_UNREACHABLE.Torok Edwin1-2/+3
Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
2009-06-30Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng1-5/+11
operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
2009-06-24Rearrange some stuff in MachineOperand and add a new TargetFlags field.Chris Lattner1-25/+29
llvm-svn: 74087
2009-06-24Fix support for inline asm input / output operand tying when operand spans ↵Evan Cheng1-11/+23
across multiple registers (e.g. two i64 operands in 32-bit mode). llvm-svn: 74053
2009-06-05Remove some unnecessary #includes.Dan Gohman1-1/+0
llvm-svn: 72948
2009-04-30Make DebugLoc independent of DwarfWriter.Argyrios Kyrtzidis1-1/+4
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable* -Remove DwarfWriter::getOrCreateSourceID -Make necessary changes for the above (fix callsites, etc.) llvm-svn: 70520
2009-04-29MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.Jakob Stoklund Olesen1-2/+4
llvm-svn: 70408
2009-04-15Fix MachineInstr::getNumExplicitOperands to countDan Gohman1-2/+2
variadic operands correctly. Patch by Jakob Stoklund Olesen! llvm-svn: 69190
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