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path: root/llvm/lib/CodeGen/MachineFunction.cpp
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2021-02-18[llvm][IR] Do not place constants with static relocations in a mergeable sectionLeonard Chan1-1/+1
This patch provides two major changes: 1. Add getRelocationInfo to check if a constant will have static, dynamic, or no relocations. (Also rename the original needsRelocation to needsDynamicRelocation.) 2. Only allow a constant with no relocations (static or dynamic) to be placed in a mergeable section. This will allow unused symbols that contain static relocations and happen to fit in mergeable constant sections (.rodata.cstN) to instead be placed in unique-named sections if -fdata-sections is used and subsequently garbage collected by --gc-sections. See https://lists.llvm.org/pipermail/llvm-dev/2021-February/148281.html. Differential Revision: https://reviews.llvm.org/D95960
2021-02-15[CodeGen] Use range-based for loops (NFC)Kazu Hirata1-8/+5
2021-01-05[NFC] Add the getSizeInBytes() interface for MachineConstantPoolValueQingShan Zhang1-4/+8
Current implementation assumes that, each MachineConstantPoolValue takes up sizeof(MachineConstantPoolValue::Ty) bytes. For PowerPC, we want to lump all the constants with the same type as one MachineConstantPoolValue to save the cost that calculate the TOC entry for each const. So, we need to extend the MachineConstantPoolValue that break this assumption. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D89108
2020-12-28[CodeGen] Use llvm::append_range (NFC)Kazu Hirata1-1/+1
2020-11-16Fix the compilation assertion due to unreachable BB pruning not deleting the ↵Victor Huang1-0/+14
associated BB from the jump tables This patch is added to remove the unreachable MBBs reference in the jump table. Differential Revisien: https://reviews.llvm.org/D90498 Reviewed by: amyk, bsaleil
2020-10-21[DebugInfo] Follow up c521e44defb5 with an API improvementJeremy Morse1-2/+7
As mentioned post-commit in D85749, the 'substituteDebugValuesForInst' method added in c521e44defb5 would be better off with a limit on the number of operands to substitute. This handles the common case of "substitute the first operand between these two differing instructions", or possibly up to N first operands.
2020-10-15Fix unused variable warning when compiling with asserts disabled.Adrian Kuegel1-2/+1
Differential Revision: https://reviews.llvm.org/D89454
2020-10-15[DebugInstrRef] Support recording of instruction reference substitutionsJeremy Morse1-0/+32
Add a table recording "substitutions" between pairs of <instruction, operand> numbers, from old pairs to new pairs. Post-isel optimizations are able to record the outcome of an optimization in this way. For example, if there were a divide instruction that generated the quotient and remainder, and it were replaced by one that only generated the quotient: $rax, $rcx = DIV-AND-REMAINDER $rdx, $rsi, debug-instr-num 1 DBG_INSTR_REF 1, 0 DBG_INSTR_REF 1, 1 Became: $rax = DIV $rdx, $rsi, debug-instr-num 2 DBG_INSTR_REF 1, 0 DBG_INSTR_REF 1, 1 We could enter a substitution from <1, 0> to <2, 0>, and no substitution for <1, 1> as it's no longer generated. This approach means that if an instruction or value is deleted once we've left SSA form, all variables that used the value implicitly become "optimized out", something that isn't true of the current DBG_VALUE approach. Differential Revision: https://reviews.llvm.org/D85749
2020-10-14[DebugInstrRef] Parse debug instruction-references from/to MIRJeremy Morse1-0/+4
This patch defines the MIR format for debug instruction references: it's an integer trailing an instruction, marked out by "debug-instr-number", much like how "debug-location" identifies the DebugLoc metadata of an instruction. The instruction number is stored directly in a MachineInstr. Actually referring to an instruction comes in a later patch, but is done using one of these instruction numbers. I've added a round-trip test and two verifier checks: that we don't label meta-instructions as generating values, and that there are no duplicates. Differential Revision: https://reviews.llvm.org/D85746
2020-09-19Fix some clang-tidy bugprone-argument-comment issuesFangrui Song1-2/+2
2020-09-18IR: Move denormal mode parsing from MachineFunction to FunctionMatt Arsenault1-14/+1
This was just inspecting the IR to begin with, and is useful to check in some places in the IR.
2020-09-14Let -basic-block-sections=labels emit basicblock metadata in a new ↵Rahman Lavaee1-27/+0
.bb_addr_map section, instead of emitting special unary-encoded symbols. This patch introduces the new .bb_addr_map section feature which allows us to emit the bits needed for mapping binary profiles to basic blocks into a separate section. The format of the emitted data is represented as follows. It includes a header for every function: | Address of the function | -> 8 bytes (pointer size) | Number of basic blocks in this function (>0) | -> ULEB128 The header is followed by a BB record for every basic block. These records are ordered in the same order as MachineBasicBlocks are placed in the function. Each BB Info is structured as follows: | Offset of the basic block relative to function begin | -> ULEB128 | Binary size of the basic block | -> ULEB128 | BB metadata | -> ULEB128 [ MBB.isReturn() OR MBB.hasTailCall() << 1 OR MBB.isEHPad() << 2 ] The new feature will replace the existing "BB labels" functionality with -basic-block-sections=labels. The .bb_addr_map section scrubs the specially-encoded BB symbols from the binary and makes it friendly to profilers and debuggers. Furthermore, the new feature reduces the binary size overhead from 70% bloat to only 12%. For more information and results please refer to the RFC: https://lists.llvm.org/pipermail/llvm-dev/2020-July/143512.html Reviewed By: MaskRay, snehasish Differential Revision: https://reviews.llvm.org/D85408
2020-08-20CodeGen: Don't drop AA metadata when splitting MachineMemOperandsMatt Arsenault1-1/+3
Assuming this is used to split a memory access into smaller pieces, the new access should still have the same aliasing properties as the original memory access. As far as I can tell, this wasn't intentionally dropped. It may be necessary to drop this if you are moving the operand outside of the bounds of the original object in such a way that it may alias another IR object, but I don't think any of the existing users are doing this. Some of the uses widen into unused alignment padding, which I think is OK.
2020-08-18[GlobalISel] Add a combine for sext_inreg(load x), c --> sextload xAmara Emerson1-1/+1
This is restricted to single use loads, which if we fold to sextloads we can find more optimal addressing modes on AArch64. This also fixes an overload the MachineFunction::getMachineMemOperand() method which was incorrectly using the MF alignment instead of the MMO alignment. Differential Revision: https://reviews.llvm.org/D85966
2020-08-13[CodeGen] In narrowExtractedVectorLoad bail out for scalable vectorsDavid Sherwood1-0/+7
In narrowExtractedVectorLoad there is an optimisation that tries to combine extract_subvector with a narrowing vector load. At the moment this produces warnings due to the incorrect calls to getVectorNumElements() for scalable vector types. I've got this working for scalable vectors too when the extract subvector index is a multiple of the minimum number of elements. I have added a new variant of the function: MachineFunction::getMachineMemOperand that copies an existing MachineMemOperand, but replaces the pointer info with a null version since we cannot currently represent scaled offsets. I've added a new test for this particular case in: CodeGen/AArch64/sve-extract-subvector.ll Differential Revision: https://reviews.llvm.org/D83950
2020-06-09[MachineVerifier] Add TiedOpsRewritten flag to fix verify two-address errorKang Zhang1-0/+1
Summary: Currently, MachineVerifier will attempt to verify that tied operands satisfy register constraints as soon as the function is no longer in SSA form. However, PHIElimination will take the function out of SSA form while TwoAddressInstructionPass will actually rewrite tied operands to match the constraints. PHIElimination runs first in the pipeline. Therefore, whenever the MachineVerifier is run after PHIElimination, it will encounter verification errors on any tied operands. This patch adds a function property called TiedOpsRewritten that will be set by TwoAddressInstructionPass and will control when the verifier checks tied operands. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D80538
2020-06-02Options for Basic Block Sections, enabled in D68063 and D73674.Sriraman Tallam1-1/+1
This patch adds clang options: -fbasic-block-sections={all,<filename>,labels,none} and -funique-basic-block-section-names. LLVM Support for basic block sections is already enabled. + -fbasic-block-sections={all, <file>, labels, none} : Enables/Disables basic block sections for all or a subset of basic blocks. "labels" only enables basic block symbols. + -funique-basic-block-section-names: Enables unique section names for basic block sections, disabled by default. Differential Revision: https://reviews.llvm.org/D68049
2020-05-19CodeGen: Use RegisterMatt Arsenault1-2/+2
2020-05-12[CodeGen] Use Align in MachineConstantPool.Craig Topper1-6/+4
2020-04-13Extend BasicBlock sections to allow specifying clusters of basic blocks in ↵Rahman Lavaee1-26/+16
the same section. Differential Revision: https://reviews.llvm.org/D76954
2020-04-13Revert "Extend BasicBlock sections to allow specifying clusters of basic blocks"Rahman Lavaee1-16/+26
This reverts commit 0d4ec16d3db3a92514e14101f635e8536c208c4f Because tests were not added to the commit.
2020-04-13Extend BasicBlock sections to allow specifying clusters of basic blocksRahman Lavaee1-26/+16
in the same section. This allows specifying BasicBlock clusters like the following example: !foo !!0 1 2 !!4 This places basic blocks 0, 1, and 2 in one section in this order, and places basic block #4 in a single section of its own.
2020-04-08MachineFunction: Copy call site info when duplicating instsVedant Kumar1-0/+5
Summary: Preserve call site info for duplicated instructions. We copy over the call site info in CloneMachineInstrBundle to avoid repeated calls to copyCallSiteInfo in CloneMachineInstr. (Alternatively, we could copy call site info higher up the stack, e.g. into TargetInstrInfo::duplicate, or even into individual backend passes. However, I don't see how that would be safer or more general than the current approach.) Reviewers: aprantl, djtodoro, dstenb Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77685
2020-04-06Allow MachineFunction to obtain non-const Function (to enable MIR-level ↵Daniel Sanders1-2/+1
debugify) Summary: To debugify MIR, we need to be able to create metadata and to do that, we need a non-const Module. However, MachineFunction only had a const reference to the Function preventing this. Reviewers: aprantl, bogner Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77439
2020-03-30[Alignment][NFC] Provide tightened up functions in SelectionDAG, ↵Guillaume Chatelet1-7/+7
MachineFunction and MachineMemOperand Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77046
2020-03-27[Alignment][NFC] MachineMemOperand::getAlign/getBaseAlignGuillaume Chatelet1-13/+12
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dschuff, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, jrtc27, atanasyan, jfb, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76925
2020-03-23[Alignment][NFC] Use TFL::getStackAlign()Guillaume Chatelet1-1/+1
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: dylanmckay, sdardis, nemanjai, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76551
2020-03-23[Alignment][NFC] Deprecate ensureMaxAlignmentGuillaume Chatelet1-1/+1
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76368
2020-03-16Basic Block Sections support in LLVM.Sriraman Tallam1-0/+55
This is the second patch in a series of patches to enable basic block sections support. This patch adds support for: * Creating direct jumps at the end of basic blocks that have fall through instructions. * New pass, bbsections-prepare, that analyzes placement of basic blocks in sections. * Actual placing of a basic block in a unique section with special handling of exception handling blocks. * Supports placing a subset of basic blocks in a unique section. * Support for MIR serialization and deserialization with basic block sections. Parent patch : D68063 Differential Revision: https://reviews.llvm.org/D73674
2020-03-09[CallSiteInfo] Enable the call site info only for -g + optimizationsDjordje Todorovic1-1/+1
Emit call site info only in the case of '-g' + 'O>0' level. Differential Revision: https://reviews.llvm.org/D75175
2020-03-07Assume ieee behavior without denormal-fp-math attributeMatt Arsenault1-9/+1
2020-02-27[CallSiteInfo] Handle bundles when updating call site infoDjordje Todorovic1-20/+40
This will address the issue: P8198 and P8199 (from D73534). The methods was not handle bundles properly. Differential Revision: https://reviews.llvm.org/D74904
2020-02-20Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""Djordje Todorovic1-1/+2
This reverts commit rGfaff707db82d. A failure found on an ARM 2-stage buildbot. The investigation is needed.
2020-02-19Reland "[DebugInfo] Enable the debug entry values feature by default"Djordje Todorovic1-2/+1
Differential Revision: https://reviews.llvm.org/D73534
2020-02-18Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""Djordje Todorovic1-1/+2
This reverts commit rGa82d3e8a6e67.
2020-02-18Reland "[DebugInfo] Enable the debug entry values feature by default"Djordje Todorovic1-2/+1
This patch enables the debug entry values feature. - Remove the (CC1) experimental -femit-debug-entry-values option - Enable it for x86, arm and aarch64 targets - Resolve the test failures - Leave the llc experimental option for targets that do not support the CallSiteInfo yet Differential Revision: https://reviews.llvm.org/D73534
2020-02-12Revert "[DebugInfo] Enable the debug entry values feature by default"Djordje Todorovic1-1/+2
This reverts commit rG9f6ff07f8a39. Found a test failure on clang-with-thin-lto-ubuntu buildbot.
2020-02-12[DebugInfo] Enable the debug entry values feature by defaultDjordje Todorovic1-2/+1
This patch enables the debug entry values feature. - Remove the (CC1) experimental -femit-debug-entry-values option - Enable it for x86, arm and aarch64 targets - Resolve the test failures - Leave the llc experimental option for targets that do not support the CallSiteInfo yet Differential Revision: https://reviews.llvm.org/D73534
2020-02-10[CSInfo] Use isCandidateForCallSiteEntry() when updating the CSInfoDjordje Todorovic1-3/+14
Use the isCandidateForCallSiteEntry(). This should mostly be an NFC, but there are some parts ensuring the moveCallSiteInfo() and copyCallSiteInfo() operate with call site entry candidates (both Src and Dest should be the call site entry candidates). Differential Revision: https://reviews.llvm.org/D74122
2020-02-04Separately track input and output denormal modeMatt Arsenault1-1/+1
AMDGPU and x86 at least both have separate controls for whether denormal results are flushed on output, and for whether denormals are implicitly treated as 0 as an input. The current DAGCombiner use only really cares about the input treatment of denormals.
2020-01-17Consolidate internal denormal flushing controlsMatt Arsenault1-0/+10
Currently there are 4 different mechanisms for controlling denormal flushing behavior, and about as many equivalent frontend controls. - AMDGPU uses the fp32-denormals and fp64-f16-denormals subtarget features - NVPTX uses the nvptx-f32ftz attribute - ARM directly uses the denormal-fp-math attribute - Other targets indirectly use denormal-fp-math in one DAGCombine - cl-denorms-are-zero has a corresponding denorms-are-zero attribute AMDGPU wants a distinct control for f32 flushing from f16/f64, and as far as I can tell the same is true for NVPTX (based on the attribute name). Work on consolidating these into the denormal-fp-math attribute, and a new type specific denormal-fp-math-f32 variant. Only ARM seems to support the two different flush modes, so this is overkill for the other use cases. Ideally we would error on the unsupported positive-zero mode on other targets from somewhere. Move the logic for selecting the flush mode into the compiler driver, instead of handling it in cc1. denormal-fp-math/denormal-fp-math-f32 are now both cc1 flags, but denormal-fp-math-f32 is not yet exposed as a user flag. -cl-denorms-are-zero, -fcuda-flush-denormals-to-zero and -fno-cuda-flush-denormals-to-zero will be mapped to -fp-denormal-math-f32=ieee or preserve-sign rather than the old attributes. Stop emitting the denorms-are-zero attribute for the OpenCL flag. It has no in-tree users. The meaning would also be target dependent, such as the AMDGPU choice to treat this as only meaning allow flushing of f32 and not f16 or f64. The naming is also potentially confusing, since DAZ in other contexts refers to instructions implicitly treating input denormals as zero, not necessarily flushing output denormals to zero. This also does not attempt to change the behavior for the current attribute. The LangRef now states that the default is ieee behavior, but this is inaccurate for the current implementation. The clang handling is slightly hacky to avoid touching the existing denormal-fp-math uses. Fixing this will be left for a future patch. AMDGPU is still using the subtarget feature to control the denormal mode, but the new attribute are now emitted. A future change will switch this and remove the subtarget features.
2020-01-13[GlobalISel] Change representation of shuffle masks in MachineOperand.Eli Friedman1-0/+6
We're planning to remove the shufflemask operand from ShuffleVectorInst (D72467); fix GlobalISel so it doesn't depend on that Constant. The change to prelegalizercombiner-shuffle-vector.mir happens because the input contains a literal "-1" in the mask (so the parser/verifier weren't really handling it properly). We now treat it as equivalent to "undef" in all contexts. Differential Revision: https://reviews.llvm.org/D72663
2019-11-19Work on cleaning up denormal mode handlingMatt Arsenault1-0/+15
Cleanup handling of the denormal-fp-math attribute. Consolidate places checking the allowed names in one place. This is in preparation for introducing FP type specific variants of the denormal-fp-mode attribute. AMDGPU will switch to using this in place of the current hacky use of subtarget features for the denormal mode. Introduce a new header for dealing with FP modes. The constrained intrinsic classes define related enums that should also be moved into this header for uses in other contexts. The verifier could use a check to make sure the denorm-fp-mode attribute is sane, but there currently isn't one. Currently, DAGCombiner incorrectly asssumes non-IEEE behavior by default in the one current user. Clang must be taught to start emitting this attribute by default to avoid regressions when this is switched to assume ieee behavior if the attribute isn't present.
2019-11-13Sink MachineFunction private method out of lineReid Kleckner1-0/+9
This method is private and only called from this file and doesn't need to be inline. Saves a TargetMachine.h include in MachineFunction.h, a popular header. The include was introduced in 98603a8153086 despite the forward decl of LLVMTargetMachine.
2019-10-31[cfi] Add flag to always generate .debug_frameDavid Candler1-0/+7
This adds a flag to LLVM and clang to always generate a .debug_frame section, even if other debug information is not being generated. In situations where .eh_frame would normally be emitted, both .debug_frame and .eh_frame will be used. Differential Revision: https://reviews.llvm.org/D67216
2019-10-28Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs"Amy Huang1-16/+4
Summary: Fixes some things from original commit at https://reviews.llvm.org/D69136. The main change is that the heap alloc marker is always stored as ExtraInfo in the machine instruction instead of in the PointerSumType because it cannot hold more than 4 pointer types. Add instruction marker to MachineInstr ExtraInfo. This does almost the same thing as Pre/PostInstrSymbols, except that it doesn't create a label until printing instructions. This allows for labels to be put around instructions that are deleted/duplicated somewhere. Use this marker to track heap alloc site call instructions. Reviewers: rnk Subscribers: MatzeB, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69536
2019-10-25Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs."Amy Huang1-4/+16
Reverting commit b85b4e5a6f8579c137fecb59a4d75d7bfb111f79 due to some buildbot failures/ out of memory errors.
2019-10-25Add an instruction marker field to the ExtraInfo in MachineInstrs.Amy Huang1-16/+4
Summary: Add instruction marker to MachineInstr ExtraInfo. This does almost the same thing as Pre/PostInstrSymbols, except that it doesn't create a label until printing instructions. This allows for labels to be put around instructions that are deleted/duplicated somewhere. Also undo the workaround in r375137. Reviewers: rnk Subscribers: MatzeB, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69136
2019-10-08[DebugInfo][If-Converter] Update call site info during the optimizationNikola Prica1-9/+25
During the If-Converter optimization pay attention when copying or deleting call instructions in order to keep call site information in valid state. Reviewers: aprantl, vsk, efriedma Reviewed By: vsk, efriedma Differential Revision: https://reviews.llvm.org/D66955 llvm-svn: 374068
2019-09-27[Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet1-1/+1
llvm-svn: 373081
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