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path: root/llvm/lib/CodeGen/HardwareLoops.cpp
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2019-07-09Revert "[HardwareLoops] NFC - move hardware loop checking code to ↵Jinsong Ji1-12/+33
isHardwareLoopProfitable()" This reverts commit d95557306585404893d610784edb3e32f1bfce18. llvm-svn: 365520
2019-07-09[HardwareLoops] NFC - move hardware loop checking code to ↵Chen Zheng1-33/+12
isHardwareLoopProfitable() Differential Revision: https://reviews.llvm.org/D64197 llvm-svn: 365497
2019-07-01[ARM] WLS/LE Code GenerationSam Parker1-0/+1
Backend changes to enable WLS/LE low-overhead loops for armv8.1-m: 1) Use TTI to communicate to the HardwareLoop pass that we should try to generate intrinsics that guard the loop entry, as well as setting the loop trip count. 2) Lower the BRCOND that uses said intrinsic to an Arm specific node: ARMWLS. 3) ISelDAGToDAG the node to a new pseudo instruction: t2WhileLoopStart. 4) Add support in ArmLowOverheadLoops to handle the new pseudo instruction. Differential Revision: https://reviews.llvm.org/D63816 llvm-svn: 364733
2019-06-28[HardwareLoops] Loop counter guard intrinsicSam Parker1-16/+105
Introduce llvm.test.set.loop.iterations which sets the loop counter and also produces an i1 after testing that the count is not zero. Differential Revision: https://reviews.llvm.org/D63809 llvm-svn: 364628
2019-06-26[HardwareLoops] NFC - move loop with irreducible control flow checking logic ↵Chen Zheng1-1/+4
to HarewareLoopInfo. llvm-svn: 364415
2019-06-26[HardwareLoops] NFC - move loop with irreducible control flow checking logic ↵Chen Zheng1-9/+1
to isHardwareLoopProfitable() llvm-svn: 364397
2019-06-19[NFC] move some hardware loop checking code to a common place for other using.Chen Zheng1-82/+10
Differential Revision: https://reviews.llvm.org/D63478 llvm-svn: 363758
2019-06-17[CodeGen] Check for HardwareLoop Latch ExitBlockSam Parker1-3/+13
The HardwareLoops pass finds exit blocks with a scevable exit count. If the target specifies to update the loop counter in a register, through a phi, we need to ensure that the exit block is a latch so that we can insert the phi with the correct value for the incoming edge. Differential Revision: https://reviews.llvm.org/D63336 llvm-svn: 363556
2019-06-07Fix for lld buildbotSam Parker1-2/+1
Removed unused (in non-debug builds) variable. llvm-svn: 362775
2019-06-07[CodeGen] Generic Hardware Loop SupportSam Parker1-0/+441
Patch which introduces a target-independent framework for generating hardware loops at the IR level. Most of the code has been taken from PowerPC CTRLoops and PowerPC has been ported over to use this generic pass. The target dependent parts have been moved into TargetTransformInfo, via isHardwareLoopProfitable, with HardwareLoopInfo introduced to transfer information from the backend. Three generic intrinsics have been introduced: - void @llvm.set_loop_iterations Takes as a single operand, the number of iterations to be executed. - i1 @llvm.loop_decrement(anyint) Takes the maximum number of elements processed in an iteration of the loop body and subtracts this from the total count. Returns false when the loop should exit. - anyint @llvm.loop_decrement_reg(anyint, anyint) Takes the number of elements remaining to be processed as well as the maximum numbe of elements processed in an iteration of the loop body. Returns the updated number of elements remaining. llvm-svn: 362774
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