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path: root/llvm/lib/CodeGen/DFAPacketizer.cpp
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2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-1/+1
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie1-1/+1
This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
2017-10-20[Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek1-0/+32
llvm-svn: 316243
2017-06-07[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko1-41/+40
warnings; other minor fixes (NFC). llvm-svn: 304954
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
2017-05-01Remove unnecessary conditions as suggested by clang-tidy. NFCGabor Horvath1-4/+2
Patch by: Gergely Angeli! Differential Revision: https://reviews.llvm.org/D31936 llvm-svn: 301807
2016-08-19[Packetizer] Add debugging code to stop packetization after N instructionsKrzysztof Parzyszek1-0/+21
llvm-svn: 279325
2016-07-14Add debugging code to the packetizerKrzysztof Parzyszek1-0/+25
llvm-svn: 275455
2016-05-27Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer1-4/+6
Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982
2016-03-08Add DAG mutation interface to the DFA packetizerKrzysztof Parzyszek1-0/+24
llvm-svn: 262930
2016-02-27CodeGen: Update DFAPacketizer API to take MachineInstr&, NFCDuncan P. N. Exon Smith1-9/+10
In all but one case, change the DFAPacketizer API to take MachineInstr& instead of MachineInstr*. In DFAPacketizer::endPacket(), take MachineBasicBlock::iterator. Besides cleaning up the API, this is in search of PR26753. llvm-svn: 262142
2016-02-22Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith1-1/+1
This reverts commit r261504, since it's not obvious the new name is better: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html I'll recommit if we get consensus that it's the right direction. llvm-svn: 261567
2016-02-21CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFCDuncan P. N. Exon Smith1-1/+1
Delete MachineInstr::getIterator(), since the term "iterator" is overloaded when talking about MachineInstr. - Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so that ilist_node::getIterator() is still available. - Add it back as MachineInstr::getInstrIterator(). This matches the naming in MachineBasicBlock. - Add MachineInstr::getBundleIterator(). This is explicitly called "bundle" (not matching MachineBasicBlock) to disintinguish it clearly from ilist_node::getIterator(). - Update all calls. Some of these I switched to `auto` to remove boiler-plate, since the new name is clear about the type. There was one call I updated that looked fishy, but it wasn't clear what the right answer was. This was in X86FrameLowering::inlineStackProbe(), added in r252578 in lib/Target/X86/X86FrameLowering.cpp. I opted to leave the behaviour unchanged, but I'll reply to the original commit on the list in a moment. llvm-svn: 261504
2016-01-14[Packetizer] Code cleanup, NFCKrzysztof Parzyszek1-55/+54
llvm-svn: 257805
2015-12-16[Packetizer] Add a check whether an instruction should be packetized nowKrzysztof Parzyszek1-2/+3
Add a function VLIWPacketizerList::shouldAddToPacket, which will allow specific implementations to decide if it is profitable to add given instruction to the current packet. llvm-svn: 255780
2015-12-14[Packetizer] Add AliasAnalysis as a parameter to the packetizerKrzysztof Parzyszek1-7/+11
This will make the depedence graph more accurate if an alias analysis is provided. If nullptr is specified in its place, the behavior will remain as it is currently. llvm-svn: 255540
2015-11-22Avoid dependency between TableGen and CodeGenKrzysztof Parzyszek1-0/+27
Duplicate a few common definitions between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp to avoid including files from CodeGen in TableGen. llvm-svn: 253820
2015-11-21Hexagon V60/HVX DFA scheduler supportKrzysztof Parzyszek1-9/+27
Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. Reapply the previous patch, this time without circular dependencies. llvm-svn: 253793
2015-11-21Revert r253790: it breaks all builds for some reason.Krzysztof Parzyszek1-30/+9
llvm-svn: 253791
2015-11-21Hexagon V60/HVX DFA scheduler supportKrzysztof Parzyszek1-9/+30
Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. llvm-svn: 253790
2015-11-03ScheduleDAGInstrs: Remove IsPostRA flag; NFCMatthias Braun1-6/+5
ScheduleDAGInstrs doesn't behave differently before or after register allocation. It was only used in a method of MachineSchedulerBase which behaved differently in MachineScheduler/PostMachineScheduler. Change this to let MachineScheduler/PostMachineScheduler just pass in a parameter to that function. The order of the LiveIntervals* and bool RemoveKillFlags paramters have been switched to make out-of-tree code fail instead of unintentionally passing a value intended for the IsPostRA flag to the (previously following and default initialized) RemoveKillFlags. Differential Revision: http://reviews.llvm.org/D14245 llvm-svn: 251883
2015-10-09CodeGen: Remove a few more ilist iterator implicit conversions, NFCDuncan P. N. Exon Smith1-1/+1
llvm-svn: 249875
2015-06-23Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko1-1/+1
Apparently, the style needs to be agreed upon first. llvm-svn: 240390
2015-06-19Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko1-1/+1
The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
2014-10-14Remove the TargetMachine from DFAPacketizer since it was onlyEric Christopher1-2/+2
being used to grab subtarget specific things that we can grab from the MachineFunction anyhow. llvm-svn: 219650
2014-10-09Remove unused argument to CreateTargetScheduleState and changeEric Christopher1-1/+1
the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
2014-08-20Cleanup: Delete seemingly unused reference to MachineDominatorTree from ↵Alexey Samsonov1-9/+8
ScheduleDAGInstrs. llvm-svn: 216124
2014-08-20Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov1-1/+1
Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI constructor call. It is undefined behavior to take references to these values. This bug is reported by UBSan. llvm-svn: 216118
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-1/+1
information and update all callers. No functional change. llvm-svn: 214781
2014-04-14[C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper1-2/+2
instead of comparing to nullptr. llvm-svn: 206142
2014-03-07[C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper1-1/+1
class. llvm-svn: 203220
2013-08-23mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr ↵Andrew Trick1-1/+2
count. This fixes a pathological compile time problem with very large blocks and lots of scheduling boundaries. llvm-svn: 189116
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth1-2/+2
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-06-22Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel1-2/+2
Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 159027
2012-06-18Allow up to 64 functional units per processor itinerary.Hal Finkel1-2/+2
This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 158679
2012-05-01Target independent Hexagon Packetizer fix.Sirish Pande1-55/+36
llvm-svn: 155947
2012-04-23Temporarily revert r155364 until the upstream review can complete, perChandler Carruth1-36/+55
the stated developer policy. llvm-svn: 155373
2012-04-23Hexagon Packetizer's target independent fix.Sirish Pande1-55/+36
llvm-svn: 155364
2012-04-18This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth1-34/+55
commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. llvm-svn: 155047
2012-04-12HexagonPacketizer patch.Sirish Pande1-55/+34
llvm-svn: 154616
2012-03-07Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick1-18/+12
llvm-svn: 152262
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick1-1/+1
implement their own MachineScheduler. llvm-svn: 152261
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick1-4/+4
We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick1-1/+3
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
2012-02-23Strip a layer of boilerplate from the VLIWPacketizer by storing the ↵Benjamin Kramer1-18/+8
scheduler as an opaque pointer. llvm-svn: 151252
2012-02-15Fix library visibility problems with VLIWPacketizer.Andrew Trick1-6/+19
The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface. llvm-svn: 150633
2012-02-15Don't expose DefaultVLIWSchedulerAndrew Trick1-1/+1
llvm-svn: 150619
2012-02-15Generic "VLIW" packetizer based on a DFA generated from target itinerary.Andrew Trick1-0/+147
Patch by Sundeep! llvm-svn: 150607
2011-12-06use space star instead of star spaceSebastian Pop1-9/+9
llvm-svn: 145944
2011-12-06add missing point at the end of sentencesSebastian Pop1-6/+6
llvm-svn: 145943
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