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2023-01-05[AMDGPU] Add .uniform_work_group_size metadata to v5Vang Thao1-0/+3
Amdgpu kernel with function attribute "uniform-work-group-size"="true" requires uniform work group size (i.e. each dimension of global size is a multiple of corresponding dimension of work group size). hipExtModuleLaunchKernel allows to launch HIP kernel with non-uniform workgroup size, which makes it necessary for runtime to check and enforce uniform workgroup size if kernel requires it. To let runtime be able to enforce that, this metadata is needed to indicate that the kernel requires uniform workgroup size. Reviewed By: kzhuravl, arsenm Differential Revision: https://reviews.llvm.org/D141012
2022-12-20[Support] Move TargetParsers to new componentArchibald Elliott1-0/+1
This is a fairly large changeset, but it can be broken into a few pieces: - `llvm/Support/*TargetParser*` are all moved from the LLVM Support component into a new LLVM Component called "TargetParser". This potentially enables using tablegen to maintain this information, as is shown in https://reviews.llvm.org/D137517. This cannot currently be done, as llvm-tblgen relies on LLVM's Support component. - This also moves two files from Support which use and depend on information in the TargetParser: - `llvm/Support/Host.{h,cpp}` which contains functions for inspecting the current Host machine for info about it, primarily to support getting the host triple, but also for `-mcpu=native` support in e.g. Clang. This is fairly tightly intertwined with the information in `X86TargetParser.h`, so keeping them in the same component makes sense. - `llvm/ADT/Triple.h` and `llvm/Support/Triple.cpp`, which contains the target triple parser and representation. This is very intertwined with the Arm target parser, because the arm architecture version appears in canonical triples on arm platforms. - I moved the relevant unittests to their own directory. And so, we end up with a single component that has all the information about the following, which to me seems like a unified component: - Triples that LLVM Knows about - Architecture names and CPUs that LLVM knows about - CPU detection logic for LLVM Given this, I have also moved `RISCVISAInfo.h` into this component, as it seems to me to be part of that same set of functionality. If you get link errors in your components after this patch, you likely need to add TargetParser into LLVM_LINK_COMPONENTS in CMake. Differential Revision: https://reviews.llvm.org/D137838
2022-12-16[BinaryFormat] Use std::optional instead of llvm::Optional (NFC)Kazu Hirata1-1/+1
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-13[AMDGPU] Add `.workgroup_processor_mode` to v5 MDPierre van Houtryve1-0/+2
Adds Workgroup Processor Mode (WGP) to the HSA Metadata for Code Object v5/GFX10+. The field is already present as an asm directive and in the compute program resource register but is also needed in the MD. Reviewed By: kzhuravl Differential Revision: https://reviews.llvm.org/D139931
2022-12-06[llvm] Don't include STLForwardCompat.h (NFC)Kazu Hirata1-1/+0
STLForwardCompat.h defines remove_cvref and remove_cvref_t. These source files use neither one of those.
2022-12-05[DebugInfo] llvm::Optional => std::optionalFangrui Song1-3/+4
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02[llvm] Use std::nullopt instead of None (NFC)Kazu Hirata1-6/+6
This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-11-17[BinaryFormat] Add LoongArchWANG Xuerui1-0/+3
Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D138018
2022-10-27[ObjectYAML] Add support for DXContainer HASHChris Bieneman1-1/+6
DXContainer files contain a part that has an MD5 of the generated shader. This adds support to the ObjectYAML tooling to expand the hash part data and hash iteself in preparation for adding hashing support to DirectX code generation. Reviewed By: python3kgae Differential Revision: https://reviews.llvm.org/D136632
2022-09-29[NFC] Refactor DXContainer to support more partsChris Bieneman2-0/+26
This patch refactors some of the DXContainer Object and YAML code to make it easier to add more part parsing. DXContainer has a whole bunch of constant values, so I've added a DXContainerConstants.def file which will grow with constant definitions, but starts with just part identifiers. I've also added a utility to parse the part magic string into an enum, and converted the code to use that utility and the enum instead of the part literal string. Reviewed By: lhames Differential Revision: https://reviews.llvm.org/D133980
2022-09-28[iwyu] Move <cmath> out of llvm/Support/MathExtras.hserge-sans-paille1-0/+2
Interestingly, MathExtras.h doesn't use <cmath> declaration, so move it out of that header and include it when needed. No functional change intended, but there's no longer a transitive include fromMathExtras.h to cmath.
2022-09-05[ARM64EC 1/?] Add parsing support to llvm-objdump/llvm-readobj.Eli Friedman1-0/+5
This is the first patch of a patchset to add initial support for ARM64EC. Basic documentation is available at https://docs.microsoft.com/en-us/windows/uwp/porting/arm64ec-abi . (Discourse post: https://discourse.llvm.org/t/initial-patches-for-arm64ec-windows-11-now-posted/62449 .) The file format for ARM64EC is basically identical to normal ARM64. There are a few extra sections, but the existing code for reading ARM64 object files just works. Differential Revision: https://reviews.llvm.org/D125411
2022-08-24Add MachO MH_FILESET support to objdumpPeter Cooper1-0/+2
https://reviews.llvm.org/D131909
2022-08-08[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFCFangrui Song1-2/+2
With C++17 there is no Clang pedantic warning or MSVC C5051.
2022-07-18[AMDGPU] Add the uses_dynamic_stack field to the kernel descriptor and the ↵Abinav Puthan Purayil1-0/+3
kernel metadata map This change introduces the dynamic stack boolean field to code-object-v3 and above under the code properties of the kernel descriptor and under the kernel metadata map of NT_AMDGPU_METADATA. This field corresponds to the is_dynamic_callstack field of amd_kernel_code_t. Differential Revision: https://reviews.llvm.org/D128344
2022-06-01[Binary] Promote OffloadBinary to inherit from BinaryJoseph Huber1-0/+5
We use the `OffloadBinary` to create binary images of offloading files and their corresonding metadata. This patch changes this to inherit from the base `Binary` class. This allows us to create and insepect these more generically. This patch includes all the necessary glue to implement this as a new binary format, along with added the magic bytes we use to distinguish the offloading binary to the `file_magic` implementation. Reviewed By: tra Differential Revision: https://reviews.llvm.org/D126812
2022-05-27[WebAssembly] Consolidate sectionTypeToString in BinaryFormat [NFC]Derek Schuff1-2/+27
Currently there are 2 duplicate implementation, and I want to add a use in a 3rd place. Combine them in lib/BinaryFormat so they can be shared. Also update toString for symbol and reloc types to use StringRef Differential Revision: https://reviews.llvm.org/D126553
2022-05-03Fix DXBC magic parsingChris Bieneman1-1/+1
This gets identify_magic working correctly for DXContainer files
2022-05-02[Object][DX] Identify DXBC file magicChris Bieneman1-0/+5
This adds support to llvm::identify_magic to detect DXBC and classify it as the dxcontainer format.
2022-03-14[CUDA] Add CUDA fatbinary magicJoseph Huber1-0/+4
Nvidia uses fatbinaries to bundle all of their device code. This patch adds the magic number "0x50ed55ba" used in their propeitary format to the list of magic identifies. This is technically undocumented and could unlikely be changed by Nvidia in the future. Reviewed By: tra Differential Revision: https://reviews.llvm.org/D120932
2022-02-25[AMDGPU][NFC]: Emit metadata for hidden_heap_v1 kernargChangpeng Fang1-2/+2
Summary: Emit metadata for hidden_heap_v1 kernarg Reviewers: sameerds, b-sumner Fixes: SWDEV-307188 Differential Revision: https://reviews.llvm.org/D119027
2022-02-21[COFF] Move section name encoding into BinaryFormatNicolas Miller2-0/+58
Large COFF section names are moved into the string table and the section header field is the offset into the string table encoded in ASCII for offset smaller than 7 digits and in base64 for larger offsets. The operation of taking the string table offsets is done in a few places in the codebase, so it is helpful to move this operation into `BinaryFormat` so that it can be shared everywhere it's done. So this patch takes the implementation of this operation from `llvm/lib/MC/WinCOFFObjectWriter.cpp` and moves it into `BinaryFormat`. Reviewed By: jhenderson, rnk Differential Revision: https://reviews.llvm.org/D118793
2022-01-31AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit ↵Changpeng Fang1-0/+13
kernel args Summary: Add code object v5 support (deafult is still v4) Generate metadata for implicit kernel args for the new ABI Set the metadata version to be 1.2 Reviewers: t-tye, b-sumner, arsenm, and bcahoon Fixes: SWDEV-307188, SWDEV-307189 Differential Revision: https://reviews.llvm.org/D118272
2022-01-26Cleanup headers for BinaryFormatserge-sans-paille3-5/+8
A few header removal, some forward declarations. As usual, this can break your build due to false dependencies, the most notable change are: - "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" no longer includes "llvm/BinaryFormat/MsgPackDocument.h" The impact on generated preprocessed lines for LLVMBinaryFormat is pretty nice: $ clang++ -E -Iinclude -I../llvm/include ../llvm/lib/BinaryFormat/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l before this patch: 705281 after this patch: 751456 Discourse thread on the topic: https://llvm.discourse.group/t/include-what-you-use-include-cleanup
2022-01-19[AIX] identify big archive magic as archive.zhijian1-1/+4
Summary: identify big archive magic as archive. Reviewers: Hubert Tong Differential Revision: https://reviews.llvm.org/D117511
2021-12-11Use llvm::any_of and llvm::all_of (NFC)Kazu Hirata1-5/+1
2021-08-11[llvm][clang][NFC] updates inline licence infoChristopher Di Bella1-4/+3
Some files still contained the old University of Illinois Open Source Licence header. This patch replaces that with the Apache 2 with LLVM Exception licence. Differential Revision: https://reviews.llvm.org/D107528
2021-07-20[SystemZ][z/OS] Add GOFF support to file magic identificationAnirudh Prasad1-0/+5
- This patch adds in the GOFF format to the file magic identification logic in LLVM - Currently, for the object file support, GOFF is marked as having as an error - However, this is only temporary until https://reviews.llvm.org/D98437 is merged in Reviewed By: abhina.sreeskantharajan Differential Revision: https://reviews.llvm.org/D105993
2021-07-19[elfabi] Prepare elfabi/ifs merging.Haowei Wu2-0/+569
This change implements unified text stub format and command line interface proposed in the elfabi/ifs merge plan. Differential Revision: https://reviews.llvm.org/D99399
2021-07-19[WebAssembly] Support R_WASM_MEMORY_ADDR_TLS_SLEB64 for wasm64Wouter van Oortmerssen1-0/+1
Also fixed TLS tests swapping addr & value in store op Differential Revision: https://reviews.llvm.org/D106096
2021-07-15[AIX][XCOFF][Bug-Fixed] parse the parameter type of the traceback tablezhijian1-1/+9
Summary: in the function PPCFunctionInfo::getParmsType(), there is if (Bits > 31 || (Bits > 30 && (Elt != FixedType || hasVectorParms()))) when the Bit is 31 and the Elt is not FixedType(for example the Elt is FloatingType) , the 31th bit will be not encoded, it leave the bit as zero, when the function Expected<SmallString<32>> XCOFF::parseParmsType() the original implement **// unsigned ParmsNum = FixedParmsNum + FloatingParmsNum; while (Bits < 32 && ParsedNum < ParmsNum) { ... }//** it will look the 31 bits (zero) as FixedType. which should be FloatingType, and get a error. Reviewers: Jason Liu,ZarkoCA Differential Revision: https://reviews.llvm.org/D105023
2021-06-17[WebAssembly] Rename event to tagHeejin Ahn1-2/+2
We recently decided to change 'event' to 'tag', and 'event section' to 'tag section', out of the rationale that the section contains a generalized tag that references a type, which may be used for something other than exceptions, and the name 'event' can be confusing in the web context. See - https://github.com/WebAssembly/exception-handling/issues/159#issuecomment-857910130 - https://github.com/WebAssembly/exception-handling/pull/161 Reviewed By: tlively Differential Revision: https://reviews.llvm.org/D104423
2021-06-14[AIX][XCOFF] emit vector info of traceback table.zhijian1-6/+119
Summary: emit vector info of traceback table. Reviewers: Jason Liu,Hubert Tong Differential Revision: https://reviews.llvm.org/D93659
2021-06-05MsgPackReader.cpp - add missing implicit MathExtras.h header dependency. NFCI.Simon Pilgrim1-0/+1
Noticed while investigating if we can remove an unnecessary MathExtras.h include from SmallVector.h
2021-03-25[NFC] Reordering parameters in getFile and getFileOrSTDINAbhina Sreeskantharajan1-1/+2
In future patches I will be setting the IsText parameter frequently so I will refactor the args to be in the following order. I have removed the FileSize parameter because it is never used. ``` static ErrorOr<std::unique_ptr<MemoryBuffer>> getFile(const Twine &Filename, bool IsText = false, bool RequiresNullTerminator = true, bool IsVolatile = false); static ErrorOr<std::unique_ptr<MemoryBuffer>> getFileOrSTDIN(const Twine &Filename, bool IsText = false, bool RequiresNullTerminator = true); static ErrorOr<std::unique_ptr<MB>> getFileAux(const Twine &Filename, uint64_t MapSize, uint64_t Offset, bool IsText, bool RequiresNullTerminator, bool IsVolatile); static ErrorOr<std::unique_ptr<WritableMemoryBuffer>> getFile(const Twine &Filename, bool IsVolatile = false); ``` Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D99182
2021-03-08[WebAssembly] Add new relocation for location relative dataYuta Saito1-0/+1
This `R_WASM_MEMORY_ADDR_SELFREL_I32` relocation represents an offset between its relocating address and the symbol address. It's very similar to `R_X86_64_PC32` but restricted to be used for only data segments. ``` S + A - P ``` A: Represents the addend used to compute the value of the relocatable field. P: Represents the place of the storage unit being relocated. S: Represents the value of the symbol whose index resides in the relocation entry. Proposal: https://github.com/WebAssembly/tool-conventions/issues/162 Differential Revision: https://reviews.llvm.org/D96659
2021-03-05Reapply "[DebugInfo] Add new instruction and DIExpression operator for ↵Stephen Tozer1-0/+3
variadic debug values" Rewrites test to use correct architecture triple; fixes incorrect reference in SourceLevelDebugging doc; simplifies `spillReg` behaviour so as to not be dependent on changes elsewhere in the patch stack. This reverts commit d2000b45d033c06dc7973f59909a0ad12887ff51.
2021-03-04Revert "[DebugInfo] Add new instruction and DIExpression operator for ↵Stephen Tozer1-3/+0
variadic debug values" This reverts commit d07f106f4a48b6e941266525b6f7177834d7b74e.
2021-03-04[DebugInfo] Add new instruction and DIExpression operator for variadic debug ↵gbtozers1-0/+3
values This patch adds a new instruction that can represent variadic debug values, DBG_VALUE_VAR. This patch alone covers the addition of the instruction and a set of basic code changes in MachineInstr and a few adjacent areas, but does not correctly handle variadic debug values outside of these areas, nor does it generate them at any point. The new instruction is similar to the existing DBG_VALUE instruction, with the following differences: the operands are in a different order, any number of values may be used in the instruction following the Variable and Expression operands (these are referred to in code as “debug operands”) and are indexed from 0 so that getDebugOperand(X) == getOperand(X+2), and the Expression in a DBG_VALUE_VAR must use the DW_OP_LLVM_arg operator to pass arguments into the expression. The new DW_OP_LLVM_arg operator is only valid in expressions appearing in a DBG_VALUE_VAR; it takes a single argument and pushes the debug operand at the index given by the argument onto the Expression stack. For example the sub-expression `DW_OP_LLVM_arg, 0` has the meaning “Push the debug operand at index 0 onto the expression stack.” Differential Revision: https://reviews.llvm.org/D82363
2021-01-15[Debuginfo][DW_OP_implicit_pointer] (1/7) Support for ↵Alok Kumar Sharma1-0/+3
DW_OP_LLVM_implicit_pointer New dwarf operator DW_OP_LLVM_implicit_pointer is introduced (present only in LLVM IR) This operator is required as it is different than DWARF operator DW_OP_implicit_pointer in representation and specification (number and types of operands) and later can not be used as multiple level. Reviewed By: aprantl Differential Revision: https://reviews.llvm.org/D84113
2020-12-16[XCOFF][AIX] Emit EH information in traceback tablediggerlin1-0/+25
SUMMARY: In order for the runtime on AIX to find the compact unwind section(EHInfo table), we would need to set the following on the traceback table: The 6th byte's longtbtable field to true to signal there is an Extended TB Table Flag. The Extended TB Table Flag to be 0x08 to signal there is an exception handling info presents. Emit the offset between ehinfo TC entry and TOC base after all other optional portions of traceback table. The patch is authored by Jason Liu. Reviewers: David Tenty, Digger Lin Differential Revision: https://reviews.llvm.org/D92766
2020-12-11[AIX][XCOFF] emit traceback table for function in aixdiggerlin1-0/+53
SUMMARY: 1. added a new option -xcoff-traceback-table to control whether generate traceback table for function. 2. implement the functionality of emit traceback table of a function. Reviewers: hubert.reinterpretcast, Jason Liu Differential Revision: https://reviews.llvm.org/D92398
2020-12-03[Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth.Ahmed Bougacha1-1/+1
This also teaches MachO writers/readers about the MachO cpu subtype, beyond the minimal subtype reader support present at the moment. This also defines a preprocessor macro to allow users to distinguish __arm64__ from __arm64e__. arm64e defaults to an "apple-a12" CPU, which supports v8.3a, allowing pointer-authentication codegen. It also currently defaults to ios14 and macos11. Differential Revision: https://reviews.llvm.org/D87095
2020-12-03arm64: count Triple::aarch64_32 as an aarch64 target and enable leaf frame ↵Tim Northover1-4/+2
pointers
2020-11-13[WebAssembly] Added R_WASM_FUNCTION_OFFSET_I64 for use with DWARF DW_AT_low_pcWouter van Oortmerssen1-0/+1
Needed for wasm64, see discussion in https://reviews.llvm.org/D91203 Differential Revision: https://reviews.llvm.org/D91395
2020-11-13[WebAssembly] Add new relocation type for TLS data symbolsSam Clegg1-0/+1
These relocations represent offsets from the __tls_base symbol. Previously we were just using normal MEMORY_ADDR relocations and relying on the linker to select a segment-offset rather and absolute value in Symbol::getVirtualAddress(). Using an explicit relocation type allows allow us to clearly distinguish absolute from relative relocations based on the relocation information alone. One place this is useful is being able to reject absolute relocation in the PIC case, but still accept TLS relocations. Differential Revision: https://reviews.llvm.org/D91276
2020-11-13llvmbuildectomy - replace llvm-build by plain cmakeserge-sans-paille2-22/+3
No longer rely on an external tool to build the llvm component layout. Instead, leverage the existing `add_llvm_componentlibrary` cmake function and introduce `add_llvm_component_group` to accurately describe component behavior. These function store extra properties in the created targets. These properties are processed once all components are defined to resolve library dependencies and produce the header expected by llvm-config. Differential Revision: https://reviews.llvm.org/D90848
2020-10-27msgpack: Improve error for empty nodeSebastian Neubauer1-1/+2
2020-10-13[WebAssembly] Added .tabletype to asm and multiple table support in obj filesPaulo Matos1-0/+2
Adds more testing in basic-assembly.s and a new test tables.s. Adds support to yaml reading and writing of tables as well. Differential Revision: https://reviews.llvm.org/D88815
2020-09-18DebugInfo: Cleanup RLE dumping, using a length-constrained DataExtractor ↵David Blaikie1-0/+11
rather than carrying the end offset separately