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path: root/clang/lib/Sema/SemaChecking.cpp
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2021-10-24Use llvm::is_contained (NFC)Kazu Hirata1-6/+1
2021-10-20[Sema, StaticAnalyzer] Use StringRef::contains (NFC)Kazu Hirata1-2/+1
2021-10-18[RISCV] Split RISCV vector builtins into their own file and namespace.Craig Topper1-122/+122
Similar to SVE, this separates the RVV builtlins into their own region of builtin IDs. Only those IDs are allowed to be used by the builtin_alias attribute now. Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D111923
2021-10-13[PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameterKamau Bridgeman1-2/+1
The builtin __rlwnm is currently constrained to accept only constants for the shift parameter but the instructions emitted for it have no such constraint, this patch allows the builtins to accept variable shift. Reviewed By: NeHuang, amyk Differential Revision: https://reviews.llvm.org/D111229
2021-10-12[PowerPC] Allow MMA built-ins to accept restrict and volatile qualified pointersAhsan Saghir1-7/+17
This patch allows MMA built-ins on PowerPC to accept restrict and volatile qualified pointers. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D106550
2021-10-05[PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation unitsKamau Bridgeman1-4/+28
This patch allows the use of __vector_quad and __vector_pair, PPC MMA builtin types, on all PowerPC 64-bit compilation units. When these types are made available the builtins that use them automatically become available so semantic checking for mma and pair vector memop __builtins is also expanded to ensure these builtin function call are only allowed on Power10 and new architectures. All related test cases are updated to ensure test coverage. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D109599
2021-10-04[PowerPC] Fix to guard fetch and cas 64-bit builtin versionsKamau Bridgeman1-0/+5
The builtins: `__compare_and_swaplp`, `__fetch_and_addlp`, ` __fetch_and_andlp`, `__fetch_and_orlp`, `__fetch_and_swaplp` are 64 bit only. This patch ensures the compiler produces an error in 32 bit mode. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D110824
2021-10-04[APInt] Stop using soft-deprecated constructors and methods in clang. NFC.Jay Foad1-2/+2
Stop using APInt constructors and methods that were soft-deprecated in D109483. This fixes all the uses I found in clang. Differential Revision: https://reviews.llvm.org/D110808
2021-10-03Unbreak hexagon-check-builtins.c due to rGb1fcca388441Dávid Bolvanský1-2/+2
2021-10-03Reland "[Clang] Extend -Wbool-operation to warn about bitwise and of bools ↵Dávid Bolvanský1-0/+14
with side effects" This reverts commit a4933f57f3f0a45e1db1075f7285f0761a80fc06. New warnings were fixed.
2021-10-03Fixed warnings in LLVM produced by -Wbitwise-instead-of-logicalDávid Bolvanský1-1/+1
2021-10-03Revert "[Clang] Extend -Wbool-operation to warn about bitwise and of bools ↵Dávid Bolvanský1-14/+0
with side effects" This reverts commit f62d18ff140f67a8776a7a3c62a75645d8d540b5. Found some cases in LLVM itself.
2021-10-03[Clang] Extend -Wbool-operation to warn about bitwise and of bools with side ↵Dávid Bolvanský1-0/+14
effects Motivation: https://arstechnica.com/gadgets/2021/07/google-pushed-a-one-character-typo-to-production-bricking-chrome-os-devices/ Warn for pattern boolA & boolB or boolA | boolB where boolA and boolB has possible side effects. Casting one operand to int is enough to silence this warning: for example (int)boolA & boolB or boolA| (int)boolB Fixes https://bugs.llvm.org/show_bug.cgi?id=51216 Differential Revision: https://reviews.llvm.org/D108003
2021-09-29[PowerPC] The builtins load8r and store8r are Power 7 plus.Stefan Pintilie1-0/+4
This patch makes sure that the builtins __builtin_ppc_load8r and __ builtin_ppc_store8r are only available for Power 7 and up. Currently the builtins seem to produce incorrect code if used for Power 6 or before. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D110653
2021-09-28[PowerPC] FP compare and test XL compat builtins.Quinn Pham1-0/+22
This patch is in a series of patches to provide builtins for compatability with the XL compiler. This patch adds builtins for compare exponent and test data class operations on floating point values. Reviewed By: #powerpc, lei Differential Revision: https://reviews.llvm.org/D109437
2021-09-27[X86][FP16] Add more builtins to avoid multi evaluation problems & add 2 ↵Wang, Pengfei1-0/+6
missed intrinsics Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D110336
2021-09-24[PowerPC] Add range check for vec_genpcvm builtinsQuinn Pham1-0/+5
This patch adds range checking for some Power10 altivec builtins. Range checking is done in SemaChecking. Reviewed By: #powerpc, lei, Conanap Differential Revision: https://reviews.llvm.org/D109780
2021-09-23[PowerPC] SemaChecking for darn family of builtinsAlbion Fung1-0/+7
The __darn family of builtins are only available on Pwr9, and only __darn_32 is available on both 64 and 32 bit, while the rest are only available on 64 bit. The patch adds sema checking for these builtins and separate the __darn_32's 32 bit test cases. Differential revision: https://reviews.llvm.org/D110282
2021-09-23[PowerPC] Add range checks for P10 Vector BuiltinsQuinn Pham1-0/+5
This patch adds range checking for some Power10 altivec builtins and changes the signature of a builtin to match documentation. For `vec_cntm`, range checking is done via SemaChecking. For `vec_splati_ins`, the second argument is masked to extract the 0th bit so that we always receive either a `0` or a `1`. Reviewed By: lei, amyk Differential Revision: https://reviews.llvm.org/D109710
2021-09-20[clang] Fix a few comment more typos to cycle botsNico Weber1-4/+4
2021-09-20Sema: relax va_start checking further for Windows AArch64Saleem Abdulrasool1-2/+16
When building in C mode, the VC runtime assumes that it can use pointer aliasing through `char *` for the parameter to `__va_start`. Relax the checks further. In theory we could keep the tests strict for non-system header code, but this takes the less strict approach as the additional check doesn't particularly end up being too much more helpful for correctness. The C++ type system is a bit stricter and requires the explicit cast which we continue to verify.
2021-08-30[X86] AVX512FP16 instructions enabling 6/6Wang, Pengfei1-0/+10
Enable FP16 complex FMA instructions. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105269
2021-08-24[X86] AVX512FP16 instructions enabling 5/6Wang, Pengfei1-0/+11
Enable FP16 FMA instructions. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105268
2021-08-22[X86] AVX512FP16 instructions enabling 4/6Wang, Pengfei1-0/+26
Enable FP16 unary operator instructions. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105267
2021-08-18[X86] AVX512FP16 instructions enabling 3/6Wang, Pengfei1-0/+38
Enable FP16 conversion instructions. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105265
2021-08-15[X86] AVX512FP16 instructions enabling 2/6Wang, Pengfei1-0/+14
Enable FP16 binary operator instructions. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105264
2021-08-12[PowerPC] Implement XL compatibility builtin __addexLei Huang1-0/+14
Add builtin and intrinsic for `__addex`. This patch is part of a series of patches to provide builtins for compatibility with the XL compiler. Reviewed By: stefanp, nemanjai, NeHuang Differential Revision: https://reviews.llvm.org/D107002
2021-08-02[clang][NFC] Typo fixes. Test commit.Justas Janickas1-2/+2
Fixed spelling of word "whether"
2021-07-28[clang] Evaluate strlen of strcpy argument for -Wfortify-source.Michael Benfield1-63/+77
Also introduce Expr::tryEvaluateStrLen. Differential Revision: https://reviews.llvm.org/D104887
2021-07-26[PowerPC] Changed sema checking range for tdw td builtinAlbion Fung1-1/+1
To match xlc behaviour and definition in the PowerPC ISA3.1, it is a better idea to have ibm-clang produce an error when a 0 is passed to the builtin, which will match xlc's behaviour. This patch changes the accepted range from 0 to 31 to 1 to 31. Differential revision: https://reviews.llvm.org/D106817
2021-07-26[PowerPC] Implement partial vector ld/st builtins for XL compatibilityNemanja Ivanovic1-0/+5
XL provides functions __vec_ldrmb/__vec_strmb for loading/storing a sequence of 1 to 16 bytes in big endian order, right justified in the vector register (regardless of target endianness). This is equivalent to vec_xl_len_r/vec_xst_len_r which are only available on Power9. This patch simply uses the Power9 functions when compiled for Power9, but provides a more general implementation for Power8. Differential revision: https://reviews.llvm.org/D106757
2021-07-26[SystemZ] Add support for new cpu architecture - arch14Ulrich Weigand1-0/+5
This patch adds support for the next-generation arch14 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch14 as host processor. - Assembler/disassembler support for new instructions. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10304. Note: No currently available Z system supports the arch14 architecture. Once new systems become available, the official system name will be added as supported -march name.
2021-07-22[PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibilityVictor Huang1-2/+1
This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds the builtin and intrinsic for "__stbcx". Reviewed By: nemanjai, #powerpc Differential revision: https://reviews.llvm.org/D106484
2021-07-22[AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversionJun Ma1-9/+7
According to https://godbolt.org/z/q5rME1naY and acle, we found that there are different SVE conversion behaviours between clang and gcc. It turns out that llvm does not handle SVE predicates width properly. This patch 1) checks SVE predicates width rightly with svbool_t type. 2) removes warning on svbool_t VLST <-> VLAT/GNUT conversion. 3) disables VLST <-> VLAT/GNUT conversion between SVE vectors and predicates due to different width. Differential Revision: https://reviews.llvm.org/D106333
2021-07-21[clang][Sema] removes -Wfree-nonheap-object reference param false positiveChristopher Di Bella1-2/+3
Taking the address of a reference parameter might be valid, and without CFA, false positives are going to be more trouble than they're worth. Differential Revision: https://reviews.llvm.org/D102728
2021-07-20[PowerPC] Store, load, move from and to registers related builtinsAlbion Fung1-0/+5
This patch implements store, load, move from and to registers related builtins, as well as the builtin for stfiw. The patch aims to provide feature parady with xlC on AIX. Differential revision: https://reviews.llvm.org/D105946
2021-07-20[PowerPC] Semachecking for XL compat builtin icbtQuinn Pham1-0/+3
This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds semachecking for an already implemented builtin, `__icbt`. `__icbt` is only valid for Power8 and up. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D105834
2021-07-20[PowerPC][Builtins] Added a number of builtins for compatibility with XL.Stefan Pintilie1-0/+4
Added a number of different builtins that exist in the XL compiler. Most of these builtins already exist in clang under a different name. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D104386
2021-07-16[PowerPC] Implement XL compact math builtinsLei Huang1-0/+15
Implement a subset of builtins required for compatiblilty with AIX XL compiler. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D105930
2021-07-15[PowerPC] Add PowerPC population count, reversed load and store related ↵Victor Huang1-0/+2
builtins and instrinsics for XL compatibility This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds the builtins and instrisics for population count, reversed load and store related operations. Reviewed By: nemanjai, #powerpc Differential revision: https://reviews.llvm.org/D106021
2021-07-15[PowerPC] Add PowerPC rotate related builtins and emit target independent ↵Victor Huang1-0/+34
code for XL compatibility This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds the builtins and emit target independent code for rotate related operations. Reviewed By: nemanjai, #powerpc Differential revision: https://reviews.llvm.org/D104744
2021-07-13[PowerPC] Add PowerPC compare and multiply related builtins and instrinsics ↵Victor Huang1-0/+18
for XL compatibility This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds the builtins and instrisics for compare and multiply related operations. Reviewed By: nemanjai, #powerpc Differential revision: https://reviews.llvm.org/D102875
2021-07-13[PowerPC][NFC] Power ISA features for SemacheckingVictor Huang1-8/+16
[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be used for semachecking builtin functions that are only valid for certain versions of ppc. Reviewed By: nemanjai, #powerpc Authored By: Quinn Pham <Quinn.Pham@ibm.com> Differential revision: https://reviews.llvm.org/D105501
2021-07-13Revert "[PowerPC][NFC] Power ISA features for Semachecking"Victor Huang1-16/+8
This reverts commit 10e0cdfc6526578c8892d895c0448e77cb9ba876.
2021-07-13[PowerPC][NFC] Power ISA features for SemacheckingVictor Huang1-8/+16
[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be used for semachecking builtin functions that are only valid for certain versions of ppc. Reviewed By: nemanjai, #powerpc Authored By: Quinn Pham <Quinn.Pham@ibm.com> Differential revision: https://reviews.llvm.org/D105501
2021-07-12[PowerPC] Implement trap and conversion builtins for XL compatibilityAlbion Fung1-0/+5
This patch implements trap and FP to and from double conversions. The builtins generate code that mirror what is generated from the XL compiler. Intrinsics are named conventionally with builtin_ppc, but are aliased to provide the same builtin names as the XL compiler. Differential Revision: https://reviews.llvm.org/D103668
2021-07-07Fix a failing assertion with -Wcast-alignQueen Dela Cruz1-1/+2
When there is unknown type in a struct in code compiled with -Wcast-align, the compiler crashes due to clang::ASTContext::getASTRecordLayout() failing an assert. Added check that the RecordDecl is valid before calling getASTRecordLayout().
2021-07-05[PowerPC] Implament Load and Reserve and Store Conditional BuiltinsAlbion Fung1-0/+2
This patch implaments the load and reserve and store conditional builtins for the PowerPC target, in order to have feature parody with xlC on AIX. Differential revision: https://reviews.llvm.org/D105236
2021-06-30[clang][patch] Add builtin __arithmetic_fence and option fprotect-parensMelanie Blower1-0/+27
This patch adds a new clang builtin, __arithmetic_fence. The purpose of the builtin is to provide the user fine control, at the expression level, over floating point optimization when -ffast-math (-ffp-model=fast) is enabled. The builtin prevents the optimizer from rearranging floating point expression evaluation. The new option fprotect-parens has the same effect on parenthesized expressions, forcing the optimizer to respect the parentheses. Reviewed By: aaron.ballman, kpn Differential Revision: https://reviews.llvm.org/D100118
2021-06-28Revert "[clang][patch][fpenv] Add builtin __arithmetic_fence and option ↵Melanie Blower1-27/+0
fprotect-parens" This reverts commit 4f1238e44d803b145997fa984677a6c5cdf1f417. Buildbot fails on predecessor patch
generated by cgit v1.1 at 2025-10-05 18:42:26 +0000