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2016-07-22[Profile] Enable profile merging with -fprofile-generat[=<dir>]Xinliang David Li1-1/+1
This patch enables raw profile merging for this option which is the new intended behavior. llvm-svn: 276484
2016-07-19Append clang system include path for offloading tool chains.Samuel Antao1-1/+19
Summary: This patch adds clang system include path when offloading tool chains, e.g. CUDA, are used in the current compilation. This fixes an issue detected by @rsmith in response to r275645. Reviewers: rsmith, tra Subscribers: rsmith, cfe-commits Differential Revision: https://reviews.llvm.org/D22490 llvm-svn: 275931
2016-07-18[Driver] Compute effective target triples once per job (NFCI)Vedant Kumar1-126/+187
Compute an effective target triple exactly once in ConstructJob(), and then simply pass around references to it. This eliminates wasteful re-computation of effective triples (e.g in getARMFloatABI()). Differential Revision: https://reviews.llvm.org/D22290 llvm-svn: 275895
2016-07-18Support -masm= flag for x86 assembly targets.Yunzhong Gao1-0/+19
For assembly files without .intel_syntax or .att_syntax directives, allow the -masm= flag to supply a default assembly dialect. For example, C:\TMP> type intel.s .text mov al,0 C:\TMP> clang -masm=intel -c intel.s Without this patch, one would need to pass an "-mllvm -x86-asm-syntax=" flag directly to the backend. C:\TMP> clang -mllvm --x86-asm-syntax=intel -c intel.s Differentials Review: http://reviews.llvm.org/D22285 llvm-svn: 275877
2016-07-16[Driver] Add flags for enabling both types of PGO InstrumentationSean Silva1-7/+26
The flags: Enable IR-level instrumentation -fprofile-generate or -fprofile-generate= When applying profile data: -fprofile-use=/path/to/profdata Patch by Jake VanAdrighem! Differential Revision: https://reviews.llvm.org/D21823 llvm-svn: 275668
2016-07-16Use std::string instead of StringRef when generating the auxiliar triple in ↵Samuel Antao1-1/+1
the frontend tool. llvm-svn: 275651
2016-07-15[CUDA][OpenMP] Create generic offload actionSamuel Antao1-38/+72
Summary: This patch replaces the CUDA specific action by a generic offload action. The offload action may have multiple dependences classier in “host” and “device”. The way this generic offloading action is used is very similar to what is done today by the CUDA implementation: it is used to set a specific toolchain and architecture to its dependences during the generation of jobs. This patch also proposes propagating the offloading information through the action graph so that that information can be easily retrieved at any time during the generation of commands. This allows e.g. the "clang tool” to evaluate whether CUDA should be supported for the device or host and ptas to easily retrieve the target architecture. This is an example of how the action graphs would look like (compilation of a single CUDA file with two GPU architectures) ``` 0: input, "cudatests.cu", cuda, (host-cuda) 1: preprocessor, {0}, cuda-cpp-output, (host-cuda) 2: compiler, {1}, ir, (host-cuda) 3: input, "cudatests.cu", cuda, (device-cuda, sm_35) 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_35) 5: compiler, {4}, ir, (device-cuda, sm_35) 6: backend, {5}, assembler, (device-cuda, sm_35) 7: assembler, {6}, object, (device-cuda, sm_35) 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_35)" {7}, object 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_35)" {6}, assembler 10: input, "cudatests.cu", cuda, (device-cuda, sm_37) 11: preprocessor, {10}, cuda-cpp-output, (device-cuda, sm_37) 12: compiler, {11}, ir, (device-cuda, sm_37) 13: backend, {12}, assembler, (device-cuda, sm_37) 14: assembler, {13}, object, (device-cuda, sm_37) 15: offload, "device-cuda (nvptx64-nvidia-cuda:sm_37)" {14}, object 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_37)" {13}, assembler 17: linker, {8, 9, 15, 16}, cuda-fatbin, (device-cuda) 18: offload, "host-cuda (powerpc64le-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {17}, ir 19: backend, {18}, assembler 20: assembler, {19}, object 21: input, "cuda", object 22: input, "cudart", object 23: linker, {20, 21, 22}, image ``` The changes in this patch pass the existent regression tests (keeps the existent functionality) and resulting binaries execute correctly in a Power8+K40 machine. Reviewers: echristo, hfinkel, jlebar, ABataev, tra Subscribers: guansong, andreybokhanko, tcramer, mkuron, cfe-commits, arpith-jacob, carlo.bertolli, caomhin Differential Revision: https://reviews.llvm.org/D18171 llvm-svn: 275645
2016-07-15XRay: Remove duplicate checks for xray instrumentation flagsDean Michael Berris1-10/+0
llvm-svn: 275570
2016-07-14Use hasFlag instead of hasArgDean Michael Berris1-2/+2
Summary: Fix the build to use hasFlag instead of hasArg for checking some flags. Reviewers: echristo Subscribers: mehdi_amini, cfe-commits Differential Revision: http://reviews.llvm.org/D22338 llvm-svn: 275377
2016-07-14Add C++ dependencies to xray runtimeDean Michael Berris1-2/+17
Summary: Depends on D21982 which implements the in-memory logging implementation of the XRay runtime. These additional changes also depends on D20352 which adds the bulk of XRay flags/dependencies when using the `-fxray-instrument` flag from Clang. Reviewers: echristo, rnk, aaron.ballman Subscribers: mehdi_amini, cfe-commits Differential Revision: http://reviews.llvm.org/D21983 llvm-svn: 275368
2016-07-13Add XRay flags to Clang. We implement two flags to control the XRay behaviour:Aaron Ballman1-0/+37
-fxray-instrument: enables XRay annotation of IR -fxray-instruction-threshold: configures the threshold for function size (looking at IR instructions), and allow LLVM to decide whether to add the nop sleds later on in the process. Also implements the related xray_always_instrument and xray_never_instrument function attributes. Patch by Dean Michael Berris. llvm-svn: 275330
2016-07-09[clang-cl] Add support for /ZdDavid Majnemer1-6/+13
MASM (ML.exe and ML64.exe) and older versions of MSVC (CL.exe) support a flag called /Zd which is more-or-less -gline-tables-only. It seems nicer to support this flag instead of exposing -gline-tables-only. llvm-svn: 274991
2016-07-08[OpenCL] Add missing -cl-no-signed-zeros option into driverYaxun Liu1-0/+3
Add OCL option -cl-no-signed-zeros to driver options. Also added to opencl.cl testcases. Patch by Aaron En Ye Shi. Differential Revision: http://reviews.llvm.org/D22067 llvm-svn: 274923
2016-07-07[CUDA] s/OPT_nocuda_version_chec/OPT_no_cuda_version_check/.Justin Lebar1-1/+1
Fix build breakage. llvm-svn: 274782
2016-07-07[CUDA] Check that our CUDA install supports the requested architectures.Justin Lebar1-0/+6
Summary: Raise an error if you're using a CUDA installation that's too old for the requested architectures. In practice, this means that you need a CUDA 8 install to compile for sm_6*. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21869 llvm-svn: 274781
2016-07-06[CUDA] Add utility functions for dealing with CUDA versions / architectures.Justin Lebar1-3/+4
Summary: Currently our handling of CUDA architectures is scattered all around clang. This patch centralizes it. A key advantage of this centralization is that you can now write a C++ switch on e.g. CudaArch and get a compile error if you don't handle one of the enum values. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21867 llvm-svn: 274681
2016-07-04[Sparc] Allow LEON cpu models to be selected with -mcpuJacob Baungard Hansen1-0/+8
Summary: This change exposes the recently added LEON CPUs (D19359) in the LLVM Sparc backend to Clang, allowing the cpu's to be selected using the -mcpu flag. Reviewers: jyknight, lero_chris Subscribers: jyknight, cfe-commits Differential Revision: http://reviews.llvm.org/D21683 llvm-svn: 274487
2016-07-01[Driver] Delete some dead code (NFC)Vedant Kumar1-3/+0
llvm-svn: 274379
2016-07-01Driver: support -L for MSVC toolchain under the GNU driverSaleem Abdulrasool1-0/+4
When not using clang in the CL emulation mode, honour the -L flags as additional library paths to pass to the linker invocation. llvm-svn: 274356
2016-06-29[OpenCL] Allow -cl-std and other standard -cl- options in driverYaxun Liu1-0/+34
Allow -cl-std and other standard -cl- options from cc1 to driver. Added a test for the options moved. Patch by Aaron En Ye Shi. Differential Revision: http://reviews.llvm.org/D21031 llvm-svn: 274150
2016-06-29Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC.Andrey Turetskiy1-6/+4
Differential Revision: http://reviews.llvm.org/D21641 llvm-svn: 274119
2016-06-29[Driver][AArch64] Add support for Broadcom Vulcan core.Pankaj Gode1-1/+1
Adding support for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21501 llvm-svn: 274114
2016-06-27[clang-cl] Implement support for /stdDavid Majnemer1-4/+19
/std: supports two arguments, c++14 and c++latest. Currently, c++latest maps to c++1z but this might change down the road. llvm-svn: 273841
2016-06-24Add support for musl-libc on ARM Linux.Rafael Espindola1-0/+4
Patch by Lei Zhang! llvm-svn: 273735
2016-06-23Restructure the propagation of -fPIC/-fPIE.Rafael Espindola1-4/+2
The PIC and PIE levels are not independent. In fact, if PIE is defined it is always the same as PIC. This is clear in the driver where ParsePICArgs returns a PIC level and a IsPIE boolean. Unfortunately that is currently lost and we pass two redundant levels down the pipeline. This patch keeps a bool and a PIC level all the way down to codegen. llvm-svn: 273566
2016-06-22Add support for /Ob1 and -finline-hint-functions flagsHans Wennborg1-0/+1
Add support for /Ob1 (and equivalent -finline-hint-functions), which enable inlining only for functions marked inline, either explicitly (via inline keyword, for example), or implicitly (function definition in class body, for example). This works by enabling inlining pass, and adding noinline attribute to every function not marked inline. Patch by Rudy Pons <rudy.pons@ilod.org>! Differential Revision: http://reviews.llvm.org/D20647 llvm-svn: 273440
2016-06-20Add a ENABLE_X86_RELAX_RELOCATIONS cmake option.Rafael Espindola1-1/+1
This corresponds to binutils' --enable-x86-relax-relocations. llvm-svn: 273224
2016-06-20[X86] Add -mno-iamcu option.Andrey Turetskiy1-4/+6
Add -mno-iamcu option to: 1) Countervail -miamcu option easily 2) Be compatible with GCC which supports this option Differential Revision: http://reviews.llvm.org/D21469 llvm-svn: 273147
2016-06-17Driver: introduce and use `-isystem-after` for cross-windowsSaleem Abdulrasool1-0/+7
This mirrors the many other -i*after options to insert a new system search directory at the end of the search path. This makes it possible to actually inject a search path after the resource dir. This option is similar in spirit to the /imsvc option in the clang-cl driver. This is needed to properly use the driver for Windows targets where the clang headers wrap some of the system headers. This concept is actually useful on other targets (e.g. Linux) and would be really easy to support on the core toolchain. llvm-svn: 273016
2016-06-16Compilation for Intel MCU (Part 3/3)Andrey Turetskiy1-14/+33
This is the last patch required to support compilation for Intel MCU target (e.g. Intel(R) Quark(TM) micro controller D 2000). When IAMCU triple is used: * Use IAMCU linker output format * Link with IAMCU crt objects * Link with IAMCU libraries Differential Revision: http://reviews.llvm.org/D20675 llvm-svn: 272885
2016-06-16Compilation for Intel MCU (Part 2/3)Andrey Turetskiy1-3/+14
This is the second patch required to support compilation for Intel MCU target (e.g. Intel(R) Quark(TM) micro controller D 2000). When IAMCU triple is used: * Recognize and use IAMCU GCC toolchain * Set up include paths * Forbid C++ Differential Revision: http://reviews.llvm.org/D19274 llvm-svn: 272883
2016-06-15Add support to clang-cl driver for /GS switchEtienne Bergeron1-0/+13
Summary: This patch is adding command-line support for the MSVC buffer security check. The buffer security check is turned on with the '/GS' compiler switch. https://msdn.microsoft.com/en-us/library/8dbf701c.aspx The MSVC buffer security check in implemented here: http://reviews.llvm.org/D20346 Reviewers: hans, rnk Subscribers: chrisha, cfe-commits, rnk, hans, thakis Differential Revision: http://reviews.llvm.org/D20347 llvm-svn: 272832
2016-06-13[CUDA][OpenMP] Create generic offload toolchainsSamuel Antao1-4/+4
Summary: This patch introduces the concept of offloading tool chain and offloading kind. Each tool chain may have associated an offloading kind that marks it as used in a given programming model that requires offloading. It also adds the logic to iterate on the tool chains based on the kind. Currently, only CUDA is supported, but in general a programming model (an offloading kind) may have associated multiple tool chains that require supporting offloading. This patch does not add tests - its goal is to keep the existing functionality. This patch is the first of a series of three that attempts to make the current support of CUDA more generic and easier to extend to other programming models, namely OpenMP. It tries to capture the suggestions/improvements/concerns on the initial proposal in http://lists.llvm.org/pipermail/cfe-dev/2016-February/047547.html. It only tackles the more consensual part of the proposal, i.e.does not address the problem of intermediate files bundling yet. Reviewers: ABataev, jlebar, echristo, hfinkel, tra Subscribers: guansong, Hahnfeld, andreybokhanko, tcramer, mkuron, cfe-commits, arpith-jacob, carlo.bertolli, caomhin Differential Revision: http://reviews.llvm.org/D18170 llvm-svn: 272571
2016-06-10Driver: make it easier to select the SjLj EH modelSaleem Abdulrasool1-1/+2
GCC still permits enabling the SjLj EH model. This is something which can be done on various targets. Hoist the -fsjlj-exceptions option into the driver and pass it through. This allows one to opt into the alternative EH model while retaining the default to be the target's default. Resolves PR27749! llvm-svn: 272424
2016-06-10This patch fixes target linker emulation for ARM 32 big endian.Strahinja Petrovic1-1/+1
llvm-svn: 272402
2016-06-06[mips] The default ABI depends on the CPU not the Arch on MTI and IMG vendor ↵Daniel Sanders1-0/+24
triples. Summary: 32-bit CPU's default to O32. 64-bit CPU's default to N64. The default CPU (mips32r2/mips64r2) still depends on the arch so there's no functional change when the CPU isn't specified but commands like: clang -target mips-mti-linux-gnu -mips64r2 will now default to a 64-bit ABI like our gcc toolchains do* instead of asserting in the backend**. Other vendors (including Triple::UnknownVendor) still derive the default ABI from the arch. * Although not the same one as our gcc toolchains, clang has historically defaulted to N64 where gcc defaults to N32. ** Mixing O32 and a 64-bit CPU causing assertions is a long-standing bug. Reviewers: atanasyan Subscribers: sdardis, cfe-commits Differential Revision: http://reviews.llvm.org/D21016 llvm-svn: 271884
2016-06-04Add PIE magic for NetBSD. Add tests for the correct flags forJoerg Sonnenberger1-9/+10
non-shared, PIE and shared output mode. llvm-svn: 271801
2016-06-03RAS extensions are part of ARMv8.2.Sjoerd Meijer1-0/+2
This patch enables +ras +noras to AArch64 in clang. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20283 llvm-svn: 271672
2016-06-02This adds target support and tests for Cortex-A73Sjoerd Meijer1-1/+1
Differential Revision: http://reviews.llvm.org/D20864 llvm-svn: 271507
2016-05-29Handle -Wa,--mrelax-relocations=[no|yes].Rafael Espindola1-0/+10
llvm-svn: 271162
2016-05-27[Driver] Fix driver support for color diagnosticsBruno Cardoso Lopes1-28/+12
Diagnostics that happen during driver time do not have color output support unless -fcolor-diagonostic is explicitly passed into the driver. This is not a problem for cc1 since dianostic arguments are properly handled and color is enabled by default if the terminal supports it. Make the driver behave like CC1. There are tests that already check for these flags, but for the color itself there's no sensible way to test it. Differential Revision: http://reviews.llvm.org/D20404 rdar://problem/26290980 llvm-svn: 271042
2016-05-27[mips] Compact branch policy setting.Simon Dardis1-0/+21
This patch adds the commandline option -mcompact-branches={never,optimal,always), which controls how LLVM generates compact branches for MIPSR6 targets. By default, the compact branch policy is 'optimal' where LLVM will generate the most appropriate branch for any situation. The 'never' and 'always' policy will disable or always generate compact branches wherever possible respectfully. Reviewers: dsanders, vkalintiris, atanasyan Differential Revision: http://reviews.llvm.org/D20729 llvm-svn: 271000
2016-05-27[mips] Kill 'support' for untested EABI.Daniel Sanders1-1/+1
Summary: There are no llvm backend tests* for EABI and no EABI buildbots. There were only three clang tests, all of which checked that -mabi=eabi was passed to the assembler. *There is a single backend test that specifies EABI but it actually tests MIPS16. Reviewers: atanasyan Subscribers: emaste, sdardis, atanasyan, cfe-commits Differential Revision: http://reviews.llvm.org/D20679 llvm-svn: 270998
2016-05-27Turn copies into references as suggested by clang-tidy's ↵Benjamin Kramer1-1/+1
performance-unnecessary-copy-initialization. llvm-svn: 270994
2016-05-27[OPENMP] Fixed processing of '-fopenmp-version=' option and test.Alexey Bataev1-1/+1
llvm-svn: 270962
2016-05-26[AMDGPU] Remove individual debugger options + update featuresKonstantin Zhuravlyov1-1/+2
Differential Revision: http://reviews.llvm.org/D20336 llvm-svn: 270895
2016-05-26[OPENMP] Add option '-fopenmp-version=[31|40|45]' allowing choosingAlexey Bataev1-1/+3
OpenMP version. If '-fopenmp' option is provided '-fopenmp-version=' allows to control, which version of OpenMP must be supported. Currently it affects only the value of _OPENMP define. llvm-svn: 270838
2016-05-25Revert "[AArch64] Using new TargetParser in Clang"Renato Golin1-15/+39
This reverts commit r270688 and r270689. The issue is not a random order, but a different order for some targets and others (prob. Linux vs Darwin). Reverting until we have a better fix. llvm-svn: 270691
2016-05-25[AArch64] Using new TargetParser in ClangRenato Golin1-39/+15
Using AArch64TargetParser in clang to avoid repetitive string parsing. Use TargetParser to do ARCH/CPU/ArchExt parsing instead of local implementation. Patch by Jojo Ma. llvm-svn: 270688
2016-05-24[Driver] Add support for -finline-functions and /Ob2 flagsHans Wennborg1-2/+3
-finline-functions and /Ob2 are currently ignored by Clang. The only way to enable inlining is to use the global O flags, which also enable other options, or to emit LLVM bitcode using Clang, then running opt by hand with the inline pass. This patch allows to simply use the -finline-functions flag (same as GCC) or /Ob2 in clang-cl mode to enable inlining without other optimizations. This is the first patch of a serie to improve support for the /Ob flags. Patch by Rudy Pons <rudy.pons@ilod.org>! Differential Revision: http://reviews.llvm.org/D20576 llvm-svn: 270609
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