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2022-02-02[clang][Sparc] Fix __builtin_extract_return_addr etc.Rainer Orth1-0/+34
While investigating the failures of `symbolize_pc.cpp` and `symbolize_pc_inline.cpp` on SPARC (both Solaris and Linux), I noticed that `__builtin_extract_return_addr` is a no-op in `clang` on all targets, while `gcc` has non-default implementations for arm, mips, s390, and sparc. This patch provides the SPARC implementation. For background see `SparcISelLowering.cpp` (`SparcTargetLowering::LowerReturn_32`), the SPARC psABI p.3-12, `%i7` and p.3-16/17, and SCD 2.4.1, p.3P-10, `%i7` and p.3P-15. Tested (after enabling the `sanitizer_common` tests on SPARC) on `sparcv9-sun-solaris2.11`. Differential Revision: https://reviews.llvm.org/D91607
2022-01-30[clang][AVR] Set '-fno-use-cxa-atexit' to defaultBen Shi1-6/+8
AVR is baremetal environment, so the avr-libc does not support '__cxa_atexit()'. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D118445
2022-01-28[clang][ARM] Emit warnings when PACBTI-M is used with unsupported architecturesAmilendra Kodithuwakku1-13/+32
Branch protection in M-class is supported by - Armv8.1-M.Main - Armv8-M.Main - Armv7-M Attempting to enable this for other architectures, either by command-line (e.g -mbranch-protection=bti) or by target attribute in source code (e.g. __attribute__((target("branch-protection=..."))) ) will generate a warning. In both cases function attributes related to branch protection will not be emitted. Regardless of the warning, module level attributes related to branch protection will be emitted when it is enabled via the command-line. The following people also contributed to this patch: - Victor Campos Reviewed By: chill Differential Revision: https://reviews.llvm.org/D115501
2022-01-25[clang] Remove some getPointerElementType() usesNikita Popov1-6/+8
Same cases where the call can be removed in a straightforward way.
2022-01-25[NFC] Remove uses of PointerType::getElementType()Nikita Popov1-5/+3
Instead use either Type::getPointerElementType() or Type::getNonOpaquePointerElementType(). This is part of D117885, in preparation for deprecating the API.
2022-01-19[clang][AVR] Implement '__flashN' for variables on different flash banksBen Shi1-4/+5
Reviewed By: aykevl Differential Revision: https://reviews.llvm.org/D115982
2022-01-14clang/AMDGPU: Don't set implicit arg attribute to default sizeMatt Arsenault1-7/+0
Since 2959e082e1427647e107af0b82770682eaa58fe1, we conservatively assume all inputs are enabled by default. This isn't the best interface for controlling these anyway, since it's not granular and only allows trimming the last fields.
2022-01-12[OpenCL] Set external linkage for block enqueue kernelsSven van Haastregt1-1/+1
All kernels can be called from the host as per the SPIR_KERNEL calling convention. As such, all kernels should have external linkage, but block enqueue kernels were created with internal linkage. Reported-by: Pedro Olsen Ferreira Differential Revision: https://reviews.llvm.org/D115523
2022-01-10Use a sorted array instead of a map to store AttrBuilder string attributesSerge Guelton1-4/+4
Using and std::map<SmallString, SmallString> for target dependent attributes is inefficient: it makes its constructor slightly heavier, and involves extra allocation for each new string attribute. Storing the attribute key/value as strings implies extra allocation/copy step. Use a sorted vector instead. Given the low number of attributes generally involved, this is cheaper, as showcased by https://llvm-compile-time-tracker.com/compare.php?from=5de322295f4ade692dc4f1823ae4450ad3c48af2&to=05bc480bf641a9e3b466619af43a2d123ee3f71d&stat=instructions Differential Revision: https://reviews.llvm.org/D116599
2022-01-09[clang] Use true/false instead of 1/0 (NFC)Kazu Hirata1-1/+1
Identified with modernize-use-bool-literals.
2021-12-29[clang] Use nullptr instead of 0 or NULL (NFC)Kazu Hirata1-1/+1
Identified with modernize-use-nullptr.
2021-12-16[CodeGen] Avoid more pointer element type accessesNikita Popov1-5/+5
2021-12-13[clang][amdgpu] - Choose when to promote VarDecl to address space 4.Ethan Stewart1-1/+3
There are instances where clang codegen creates stores to address space 4 in ctors, which causes a crash in llc. This store was being optimized out at opt levels > 0. For example: pragma omp declare target static const double log_smallx = log2(smallx); pragma omp end declare target This patch ensures that any global const that does not have constant initialization stays in address space 1. Note - a second patch is in the works where all global constants are placed in address space 1 during codegen and then the opt pass InferAdressSpaces will promote to address space 4 where necessary. Reviewed By: JonChesterfield Differential Revision: https://reviews.llvm.org/D115661
2021-12-08[HIPSPV] Convert HIP kernels to SPIR-V kernelsHenry Linjamäki1-4/+68
This patch translates HIP kernels to SPIR-V kernels when the HIP compilation mode is targeting SPIR-S. This involves: * Setting Cuda calling convention to CC_OpenCLKernel (which maps to SPIR_KERNEL in LLVM IR later on). * Coercing pointer arguments with default address space (AS) qualifier to CrossWorkGroup AS (__global in OpenCL). HIPSPV's device code is ultimately SPIR-V for OpenCL execution environment (as starter/default) where Generic or Function (OpenCL's private) is not supported as storage class for kernel pointer types. This leaves the CrossWorkGroup to be the only reasonable choice for HIP buffers. Reviewed By: yaxunl Differential Revision: https://reviews.llvm.org/D109818
2021-12-06Introduce _BitInt, deprecate _ExtIntAaron Ballman1-34/+35
WG14 adopted the _ExtInt feature from Clang for C23, but renamed the type to be _BitInt. This patch does the vast majority of the work to rename _ExtInt to _BitInt, which accounts for most of its size. The new type is exposed in older C modes and all C++ modes as a conforming extension. However, there are functional changes worth calling out: * Deprecates _ExtInt with a fix-it to help users migrate to _BitInt. * Updates the mangling for the type. * Updates the documentation and adds a release note to warn users what is going on. * Adds new diagnostics for use of _BitInt to call out when it's used as a Clang extension or as a pre-C23 compatibility concern. * Adds new tests for the new diagnostic behaviors. I want to call out the ABI break specifically. We do not believe that this break will cause a significant imposition for early adopters of the feature, and so this is being done as a full break. If it turns out there are critical uses where recompilation is not an option for some reason, we can consider using ABI tags to ease the transition.
2021-12-03[PowerPC] [Clang] Fix alignment adjustment of single-elemented float128Qiu Chaofan1-4/+9
This does similar thing to 6b1341e, but fixes single element 128-bit float type: `struct { long double x; }`. Reviewed By: rjmccall Differential Revision: https://reviews.llvm.org/D114937
2021-12-02Reapply "OpenMP: Start calling setTargetAttributes for generated kernels"Matt Arsenault1-30/+43
This reverts commit 25eb7fa01d7ebbe67648ea03841cda55b4239ab2. Previous buildbot failures appear to have been a fluke from a dirty build.
2021-12-01[clang][ARM] PACBTI-M frontend supportTies Stuij1-2/+20
Handle branch protection option on the commandline as well as a function attribute. One patch for both mechanisms, as they use the same underlying parsing mechanism. These are recorded in a set of LLVM IR module-level attributes like we do for AArch64 PAC/BTI (see https://reviews.llvm.org/D85649): - command-line options are "translated" to module-level LLVM IR attributes (metadata). - functions have PAC/BTI specific attributes iff the __attribute__((target("branch-protection=...))) was used in the function declaration. - command-line option -mbranch-protection to armclang targeting Arm, following this grammar: branch-protection ::= "-mbranch-protection=" <protection> protection ::= "none" | "standard" | "bti" [ "+" <pac-ret-clause> ] | <pac-ret-clause> [ "+" "bti"] pac-ret-clause ::= "pac-ret" [ "+" <pac-ret-option> ] pac-ret-option ::= "leaf" ["+" "b-key"] | "b-key" ["+" "leaf"] b-key is simply a placeholder to make it consistent with AArch64's version. In Arm, however, it triggers a warning informing that b-key is unsupported and a-key will be selected instead. - Handle _attribute_((target(("branch-protection=..."))) for AArch32 with the same grammer as the commandline options. This patch is part of a series that adds support for the PACBTI-M extension of the Armv8.1-M architecture, as detailed here: https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension The PACBTI-M specification can be found in the Armv8-M Architecture Reference Manual: https://developer.arm.com/documentation/ddi0553/latest The following people contributed to this patch: - Momchil Velikov - Victor Campos - Ties Stuij Reviewed By: vhscampos Differential Revision: https://reviews.llvm.org/D112421
2021-11-29Revert "OpenMP: Start calling setTargetAttributes for generated kernels"Matt Arsenault1-43/+30
This reverts commit 6c27d389c8a00040aad998fe959f38ba709a8750. This is failing on the buildbots
2021-11-29OpenMP: Start calling setTargetAttributes for generated kernelsMatt Arsenault1-30/+43
This wasn't setting any of the attributes the target would expect to emit for kernels.
2021-11-23Fix warning due to default switch labelYaxun (Sam) Liu1-3/+0
Fix warning due to default label in switch which covers all enumeration values
2021-11-23[HIP] Add HIP scope atomic operationsYaxun (Sam) Liu1-2/+13
Add an AtomicScopeModel for HIP and support for OpenCL builtins that are missing in HIP. Patch by: Michael Liao Revised by: Anshil Ghandi Reviewed by: Yaxun Liu Differential Revision: https://reviews.llvm.org/D113925
2021-11-08[SPIR-V] Add SPIR-V triple and clang target info.Anastasia Stulova1-9/+13
Add new triple and target info for ‘spirv32’ and ‘spirv64’ and, thus, enabling clang (LLVM IR) code emission to SPIR-V target. The target for SPIR-V is mostly reused from SPIR by derivation from a common base class since IR output for SPIR-V is mostly the same as SPIR. Some refactoring are made accordingly. Added and updated tests for parts that are different between SPIR and SPIR-V. Patch by linjamaki (Henry Linjamäki)! Differential Revision: https://reviews.llvm.org/D109144
2021-10-21[clang] Use StringRef::contains (NFC)Kazu Hirata1-1/+1
2021-10-08[X86] Check if struct is blank before getting the inner typesWang, Pengfei1-0/+3
This fixes pr52011. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D111037
2021-09-20[X86] Always check the size of SourceTy before getting the next typeWang, Pengfei1-4/+10
D109607 results in a regression in llvm-test-suite. The reason is we didn't check the size of SourceTy, so that we will return wrong SSE type when SourceTy is overlapped. Reviewed By: Meinersbur Differential Revision: https://reviews.llvm.org/D110037
2021-09-17[X86] Refactor GetSSETypeAtOffset to fix pr51813Wang, Pengfei1-75/+39
D105263 adds support for _Float16 type. It introduced a bug (pr51813) that generates a <4 x half> type instead the default double when passing blank structure by SSE registers. Although I doubt it may expose a bug somewhere other than D105263, it's good to avoid return half type when no half type in arguments. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D109607
2021-09-16[PowerPC][AIX] Add support for varargs for complex types on AIXZarko Todorovski1-29/+45
Remove the previous error and add support for special handling of small complex types as in PPC64 ELF ABI. As in, generate code to load from varargs location and pack it in a temp variable, then return a pointer to the struct. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D106393
2021-09-06[X86][mingw] Modify the alignment of __m128/__m256/__m512 vector type for mingwWang, Pengfei1-1/+2
This is a follow up patch after D78564 and D108887. Martin helped to confirm the alignment in GCC mingw is the same as the size of vector. https://reviews.llvm.org/D108887#inline-1040893 Reviewed By: mstorsjo Differential Revision: https://reviews.llvm.org/D109265
2021-09-06[Clang] Add __ibm128 type to represent ppc_fp128Qiu Chaofan1-1/+2
Currently, we have no front-end type for ppc_fp128 type in IR. PowerPC target generates ppc_fp128 type from long double now, but there's option (-mabi=(ieee|ibm)longdouble) to control it and we're going to do transition from IBM extended double-double ppc_fp128 to IEEE fp128 in the future. This patch adds type __ibm128 which always represents ppc_fp128 in IR, as what GCC did for that type. Without this type in Clang, compilation will fail if compiling against future version of libstdcxx (which uses __ibm128 in headers). Although all operations in backend for __ibm128 is done by software, only PowerPC enables support for it. There's something not implemented in this commit, which can be done in future ones: - Literal suffix for __ibm128 type. w/W is suitable as GCC documented. - __attribute__((mode(IF))) should be for __ibm128. - Complex __ibm128 type. Reviewed By: rjmccall Differential Revision: https://reviews.llvm.org/D93377
2021-08-28TypeInfo records more information about align requirementSteven Wan1-2/+2
Extend the information preserved in `TypeInfo` by replacing the `AlignIsRequired` bool flag with a three-valued enum, the enum also indicates where the alignment attribute come from, which could be helpful in determining whether the attribute should overrule. Reviewed By: rjmccall Differential Revision: https://reviews.llvm.org/D108858
2021-08-17[NFC] Migrate some callers away from Function/AttributeLists methods that ↵Arthur Eubanks1-4/+4
take an index These methods can be confusing.
2021-08-18[CFE][X86] Enable complex _Float16 supportWang, Pengfei1-0/+8
Support complex _Float16 on X86 in C/C++ following the latest X86 psABI. (https://gitlab.com/x86-psABIs) Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105331
2021-08-10[X86] AVX512FP16 instructions enabling 1/6Wang, Pengfei1-12/+62
1. Enable FP16 type support and basic declarations used by following patches. 2. Enable new instructions VMOVW and VMOVSH. Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D105263
2021-07-31[Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'Alexandros Lamprineas1-0/+14
In LLVM IR terms the ACLE type 'data512_t' is essentially an aggregate type { [8 x i64] }. When emitting code for inline assembly operands, clang tries to scalarize aggregate types to an integer of the equivalent length, otherwise it passes them by-reference. This patch adds a target hook to tell whether a given inline assembly operand is scalarizable so that clang can emit code to pass/return it by-value. Differential Revision: https://reviews.llvm.org/D94098
2021-07-17[OpaquePtr] Remove uses of CreateGEP() without element typeNikita Popov1-15/+22
Remove uses of to-be-deprecated API. In cases where the correct element type was not immediately obvious to me, fall back to explicit getPointerElementType().
2021-06-29[AVR][clang] Fix wrong calling convention in functions return struct typeBen Shi1-2/+27
According to AVR ABI (https://gcc.gnu.org/wiki/avr-gcc), returned struct value within size 1-8 bytes should be returned directly (via register r18-r25), while larger ones should be returned via an implicit struct pointer argument. Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D99237
2021-06-25[clang] Rename StringRef _lower() method calls to _insensitive()Martin Storsjö1-1/+1
This is mostly a mechanical change, but a testcase that contains parts of the StringRef class (clang/test/Analysis/llvm-conventions.cpp) isn't touched.
2021-06-08[clang] Apply MS ABI details on __builtin_ms_va_list on non-windows ↵Martin Storsjö1-1/+6
platforms on x86_64 This fixes inconsistencies in the ms_abi.c testcase. Also add a couple cases of missing double pointers in the windows part of the testcase; the outcome of building that testcase on windows hasn't changed, but the previous form of the test was imprecise (checking for "%[[STRUCT_FOO]]*" when clang actually generates "%[[STRUCT_FOO]]**"), which still used to match. Ideally this would share code with the native Windows case, but X86_64ABIInfo and WinX86_64ABIInfo aren't superclasses/subclasses of each other so it's impractical, and the code to share currently only consists of a couple lines. Differential Revision: https://reviews.llvm.org/D103837
2021-06-07[clang] Fix reading long doubles with va_arg on x86_64 mingwMartin Storsjö1-7/+2
On x86_64 mingw, long doubles are always passed indirectly as arguments (see an existing case in WinX86_64ABIInfo::classify); generalize the existing code for reading varargs - any non-aggregate type that is larger than 64 bits (which would be both long double in mingw, and __int128) are passed indirectly too. This makes reading varargs consistent with how they're passed, fixing interop with both gcc and clang callers, for long double and __int128. Differential Revision: https://reviews.llvm.org/D103452
2021-05-10[clang][AArch32] Correctly align HA arguments when passed on the stackMomchil Velikov1-1/+10
Analogously to https://reviews.llvm.org/D98794 this patch uses the `alignstack` attribute to fix incorrect passing of homogeneous aggregate (HA) arguments on AArch32. The EABI/AAPCS was recently updated to clarify how VFP co-processor candidates are aligned: https://github.com/ARM-software/abi-aa/commit/4488e34998514dc7af5507236f279f6881eede62 Differential Revision: https://reviews.llvm.org/D100853
2021-05-04[Clang][AArch64] Disable rounding of return values for AArch64Andrew Savonichev1-0/+12
If a return value is explicitly rounded to 64 bits, an additional zext instruction is emitted, and in some cases it prevents tail call optimization. As discussed in D100225, this rounding is not necessary and can be disabled. Differential Revision: https://reviews.llvm.org/D100591
2021-05-01[AMDGPU] Add options -mamdgpu-ieee -mno-amdgpu-ieeeYaxun (Sam) Liu1-0/+3
AMDGPU backend need to know whether floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE754-2008, which is conveyed by a function attribute "amdgpu-ieee". "amdgpu-ieee"="false" turns this off. Without this function attribute backend assumes it is on for compute functions. -mamdgpu-ieee and -mno-amdgpu-ieee are added to Clang to control this function attribute. By default it is on. -mno-amdgpu-ieee requires -fno-honor-nans or equivalent. Reviewed by: Matt Arsenault Differential Revision: https://reviews.llvm.org/D77013
2021-04-26[SYCL] Implement SYCL address space attributes handlingAlexey Bader1-0/+6
Default address space (applies when no explicit address space was specified) maps to generic (4) address space. Added SYCL named address spaces `sycl_global`, `sycl_local` and `sycl_private` defined as sub-sets of the default address space. Static variables without address space now reside in global address space when compile for SPIR target, unless they have an explicit address space qualifier in source code. Differential Revision: https://reviews.llvm.org/D89909
2021-04-22Temporarily revert the code part of D100981 "Delete le32/le64 targets"Fangrui Song1-0/+2
This partially reverts commit 77ac823fd285973cfb3517932c09d82e6a32f46d. Halide uses le32/le64 (https://github.com/halide/Halide/pull/5934). Temporarily brings back the code part to give them some time for migration.
2021-04-21Delete le32/le64 targetsFangrui Song1-2/+0
They are unused now. Note: NaCl is still used and is currently expected to be needed until 2022-06 (https://blog.chromium.org/2020/08/changes-to-chrome-app-support-timeline.html). Differential Revision: https://reviews.llvm.org/D100981
2021-04-15[clang][AArch64] Correctly align HFA arguments when passed on the stackMomchil Velikov1-1/+12
When we pass a AArch64 Homogeneous Floating-Point Aggregate (HFA) argument with increased alignment requirements, for example struct S { __attribute__ ((__aligned__(16))) double v[4]; }; Clang uses `[4 x double]` for the parameter, which is passed on the stack at alignment 8, whereas it should be at alignment 16, following Rule C.4 in AAPCS (https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#642parameter-passing-rules) Currently we don't have a way to express in LLVM IR the alignment requirements of the function arguments. The align attribute is applicable to pointers only, and only for some special ways of passing arguments (e..g byval). When implementing AAPCS32/AAPCS64, clang resorts to dubious hacks of coercing to types, which naturally have the needed alignment. We don't have enough types to cover all the cases, though. This patch introduces a new use of the stackalign attribute to control stack slot alignment, when and if an argument is passed in memory. The attribute align is left as an optimizer hint - it still applies to pointer types only and pertains to the content of the pointer, whereas the alignment of the pointer itself is determined by the stackalign attribute. For byval arguments, the stackalign attribute assumes the role, previously perfomed by align, falling back to align if stackalign` is absent. On the clang side, when passing arguments using the "direct" style (cf. `ABIArgInfo::Kind`), now we can optionally specify an alignment, which is emitted as the new `stackalign` attribute. Patch by Momchil Velikov and Lucas Prates. Differential Revision: https://reviews.llvm.org/D98794
2021-04-15[clang] [AArch64] Fix handling of HFAs passed to Windows variadic functionsMartin Storsjö1-8/+16
The documentation says that for variadic functions, all composites are treated similarly, no special handling of HFAs/HVAs, not even for the fixed arguments of a variadic function. Differential Revision: https://reviews.llvm.org/D100467
2021-04-14[clang] [AArch64] Fix Windows va_arg handling for larger structsMartin Storsjö1-1/+7
Aggregate types over 16 bytes are passed by reference. Contrary to the x86_64 ABI, smaller structs with an odd (non power of two) are padded and passed in registers. Differential Revision: https://reviews.llvm.org/D100374
2021-04-14[i386] Modify the alignment of __m128/__m256/__m512 vector type according ↵Liu, Chen31-2/+11
i386 abi. According to i386 System V ABI: 1. when __m256 are required to be passed on the stack, the stack pointer must be aligned on a 0 mod 32 byte boundary at the time of the call. 2. when __m512 are required to be passed on the stack, the stack pointer must be aligned on a 0 mod 64 byte boundary at the time of the call. The current method of clang passing __m512 parameter are as follow: 1. when target supports avx512, passing it with 64 byte alignment; 2. when target supports avx, passing it with 32 byte alignment; 3. Otherwise, passing it with 16 byte alignment. Passing __m256 parameter are as follow: 1. when target supports avx or avx512, passing it with 32 byte alignment; 2. Otherwise, passing it with 16 byte alignment. This pach will passing __m128/__m256/__m512 following i386 System V ABI and apply it to Linux only since other System V OS (e.g Darwin, PS4 and FreeBSD) don't want to spend any effort dealing with the ramifications of ABI breaks at present. Differential Revision: https://reviews.llvm.org/D78564
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