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path: root/clang/lib/CodeGen/TargetInfo.cpp
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2017-06-21Correct VectorCall x86 (32 bit) behavior for SSE Register AssignmentErich Keane1-72/+56
In running some internal vectorcall tests in 32 bit mode, we discovered that the behavior I'd previously implemented for x64 (and applied to x32) regarding the assignment of SSE registers was incorrect. See spec here: https://msdn.microsoft.com/en-us/library/dn375768.aspx My previous implementation applied register argument position from the x64 version to both. This isn't correct for x86, so this removes and refactors that section. Additionally, it corrects the integer/int-pointer assignments. Unlike x64, x86 permits integers to be assigned independent of position. Finally, the code for 32 bit was cleaned up a little to clarify the intent, as well as given a descriptive comment. Differential Revision: https://reviews.llvm.org/D34455 llvm-svn: 305928
2017-06-20[OpenCL] Fix OpenCL and SPIR version metadata generation.Alexey Bader1-41/+0
Summary: OpenCL and SPIR version metadata must be generated once per module instead of once per mangled global value. Reviewers: Anastasia, yaxunl Reviewed By: Anastasia Subscribers: ahatanak, cfe-commits Differential Revision: https://reviews.llvm.org/D34235 llvm-svn: 305796
2017-06-01[OpenCL] Makes kernels use the SPIR_KERNEL CC by default.Pekka Jaaskelainen1-1/+21
Rationale: OpenCL kernels are called via an explicit runtime API with arguments set with clSetKernelArg(), not as normal sub-functions. Return SPIR_KERNEL by default as the kernel calling convention to ensure the fingerprint is fixed such way that each OpenCL argument gets one matching argument in the produced kernel function argument list to enable feasible implementation of clSetKernelArg() with aggregates etc. In case we would use the default C calling conv here, clSetKernelArg() might break depending on the target-specific conventions; different targets might split structs passed as values to multiple function arguments etc. https://reviews.llvm.org/D33639 llvm-svn: 304389
2017-05-26CodeGen: Define Swift's legal vector types for AArch64, ARMArnold Schwaighofer1-0/+30
rdar://32401301 llvm-svn: 304017
2017-05-22[mips] Support `micromips` attributeSimon Atanasyan1-0/+5
This patch adds support for the `micromips` and `nomicromips` attributes for MIPS targets. Differential revision: https://reviews.llvm.org/D33363 llvm-svn: 303546
2017-05-18CodeGen: Cast alloca to expected address spaceYaxun Liu1-4/+8
Alloca always returns a pointer in alloca address space, which may be different from the type defined by the language. For example, in C++ the auto variables are in the default address space. Therefore cast alloca to the expected address space when necessary. Differential Revision: https://reviews.llvm.org/D32248 llvm-svn: 303370
2017-05-12[Hexagon] Make sure to pass empty struct arguments with nontrivial ctorsKrzysztof Parzyszek1-3/+3
Thanks to Richard Smith for the suggested fix. This fixes llvm.org/PR33009 llvm-svn: 302895
2017-05-10Reland: [mips] Impose a threshold for coercion of aggregatesPetar Jovanovic1-0/+8
Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 with minor changes (use regexp instead of the hardcoded values) to the test. llvm-svn: 302670
2017-05-09Suppress all uses of LLVM_END_WITH_NULL. NFC.Serge Guelton1-6/+4
Use variadic templates instead of relying on <cstdarg> + sentinel. This enforces better type checking and makes code more readable. Differential revision: https://reviews.llvm.org/D32550 llvm-svn: 302572
2017-05-09Revert r302547 ([mips] Impose a threshold for coercion of aggregates)Petar Jovanovic1-8/+0
Reverting Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. as it broke clang-with-lto-ubuntu builder. llvm-svn: 302555
2017-05-09[mips] Impose a threshold for coercion of aggregatesPetar Jovanovic1-0/+8
Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 llvm-svn: 302547
2017-05-05AArch64: fix weird edge case in ABI.Tim Northover1-4/+9
It turns out there are some sort-of-but-not-quite empty structs that break all the rules. For example: struct SuperEmpty { int arr[0]; }; struct SortOfEmpty { struct SuperEmpty e; }; Both of these have sizeof == 0, even in C++ mode, for GCC compatibility. The first one also doesn't occupy a register when passed by value in GNU C++ mode, unlike everything else. On Darwin, we want to ignore the lot (and especially don't want to try to use an i0 as we were). llvm-svn: 302313
2017-05-02Re-land r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Reid Kleckner1-8/+2
AttributeList" This time, I fixed, built, and tested clang. This reverts r301712. llvm-svn: 301981
2017-04-06[AMDGPU] Translate reqd_work_group_size into amdgpu_flat_work_group_sizeStanislav Mekhanoshin1-3/+8
These two attributes specify the same info in a different way. AMGPU BE only checks the latter as a target specific attribute as opposed to language specific reqd_work_group_size. This change produces amdgpu_flat_work_group_size out of reqd_work_group_size if specified. Differential Revision: https://reviews.llvm.org/D31728 llvm-svn: 299678
2017-04-03[TargetInfo] Use llvm::alignOf() instead of rewriting it. NFCI.Davide Italiano1-2/+2
llvm-svn: 299364
2017-03-21Update Clang for LLVM rename AttributeSet -> AttributeListReid Kleckner1-8/+8
llvm-svn: 298394
2017-02-11CodeGen: use # as the comment leader for ARC markerSaleem Abdulrasool1-1/+1
Use # as the comment leader for AArch64 auto-release elision marker. This is to keep it in sync with the value used in swift. When building libdispatch for Linux AArch64, the auto-release elision marker was emitted. However, ELF uses # as the comment leader while MachO accepts both ; and #. Use the common marker for it instead. llvm-svn: 294877
2017-02-08[AVR] Add support for the 'interrupt' and 'naked' attributesDylan McKay1-0/+28
Summary: This teaches clang how to parse and lower the 'interrupt' and 'naked' attributes. This allows interrupt signal handlers to be written. Reviewers: aaron.ballman Subscribers: malcolm.parsons, cfe-commits Differential Revision: https://reviews.llvm.org/D28451 llvm-svn: 294402
2017-01-13Use less byval on 32-bit Windows x86 for classes with basesReid Kleckner1-22/+38
This comes up in V8, which has a Handle template class that wraps a typed pointer, and is frequently passed by value. The pointer is stored in the base, HandleBase. This change allows us to pass the struct as a pointer instead of using byval. This avoids creating tons of temporary allocas that we copy from during call lowering. Eventually, it would be good to use FCAs here instead. llvm-svn: 291917
2017-01-05Correct Vectorcall Register passing and HVA BehaviorErich Keane1-26/+180
Front end component (back end changes are D27392). The vectorcall calling convention was broken subtly in two cases. First, it didn't properly handle homogeneous vector aggregates (HVAs). Second, the vectorcall specification requires that only the first 6 parameters be eligible for register assignment. This patch fixes both issues. Differential Revision: https://reviews.llvm.org/D27529 llvm-svn: 291041
2016-12-15Re-commit r289252 and r289285, and fix PR31374Yaxun Liu1-1/+35
llvm-svn: 289787
2016-12-14Revert 289252 (and follow-up 289285), it caused PR31374Nico Weber1-35/+1
llvm-svn: 289713
2016-12-14Replace APFloatBase static fltSemantics data members with getter functionsStephan Bergmann1-7/+7
At least the plugin used by the LibreOffice build (<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly uses those members (through inline functions in LLVM/Clang include files in turn using them), but they are not exported by utils/extract_symbols.py on Windows, and accessing data across DLL/EXE boundaries on Windows is generally problematic. Differential Revision: https://reviews.llvm.org/D26671 llvm-svn: 289647
2016-12-09Add support for non-zero null pointer for C and OpenCLYaxun Liu1-1/+35
In amdgcn target, null pointers in global, constant, and generic address space take value 0 but null pointers in private and local address space take value -1. Currently LLVM assumes all null pointers take value 0, which results in incorrectly translated IR. To workaround this issue, instead of emit null pointers in local and private address space, a null pointer in generic address space is emitted and casted to local and private address space. Tentative definition of global variables with non-zero initializer will have weak linkage instead of common linkage since common linkage requires zero initializer and does not have explicit section to hold the non-zero value. Virtual member functions getNullPointer and performAddrSpaceCast are added to TargetCodeGenInfo which by default returns ConstantPointerNull and emitting addrspacecast instruction. A virtual member function getNullPointerValue is added to TargetInfo which by default returns 0. Each target can override these virtual functions to get target specific null pointer and the null pointer value for specific address space, and perform specific translations for addrspacecast. Wrapper functions getNullPointer is added to CodegenModule and getTargetNullPointerValue is added to ASTContext to facilitate getting the target specific null pointers and their values. This change has no effect on other targets except amdgcn target. Other targets can provide support of non-zero null pointer in a similar way. This change only provides support for non-zero null pointer for C and OpenCL. Supporting for other languages will be added later incrementally. Differential Revision: https://reviews.llvm.org/D26196 llvm-svn: 289252
2016-12-07[OpenCL] Fix SPIR version generation.Alexey Bader1-2/+4
Patch by Egor Churaev (echuraev). Reviewers: Anastasia Subscribers: bader, yaxunl, cfe-commits Differential Revision: https://reviews.llvm.org/D27300 llvm-svn: 288890
2016-12-01swiftcc: Add an api to query whether a target ABI stores swifterror in a ↵Arnold Schwaighofer1-0/+21
register llvm-svn: 288394
2016-11-28IRGen: Remove all uses of CreateDefaultAlignedLoad.Peter Collingbourne1-5/+7
Differential Revision: https://reviews.llvm.org/D27157 llvm-svn: 288083
2016-11-16Add a little endian variant of TCE.Pekka Jaaskelainen1-0/+1
llvm-svn: 287112
2016-11-02regcall: Implement regcall Calling Conv in clangErich Keane1-26/+125
This patch implements the register call calling convention, which ensures as many values as possible are passed in registers. CodeGen changes were committed in https://reviews.llvm.org/rL284108. Differential Revision: https://reviews.llvm.org/D25204 llvm-svn: 285849
2016-11-02Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons1-2/+2
Reviewers: aaron.ballman, mehdi_amini, dblaikie Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D26206 llvm-svn: 285799
2016-10-12Declare WinX86_64ABIInfo to satisfy SwiftABI infoArnold Schwaighofer1-2/+8
This is minimal support that allows swift's test cases on non windows platforms to pass. rdar://28738985 llvm-svn: 284032
2016-10-02[PowerPC] Enable soft-float for PPC64, and +soft-float -> -hard-floatHal Finkel1-7/+19
Enable soft-float support on PPC64, as the backend now supports it. Also, the backend now uses -hard-float instead of +soft-float, so set the target features accordingly. Fixes PR26970. llvm-svn: 283061
2016-09-26[AMDGPU] Expose flat work group size, register and wave control attributesKonstantin Zhuravlyov1-11/+41
__attribute__((amdgpu_flat_work_group_size(<min>, <max>))) - request minimum and maximum flat work group size __attribute__((amdgpu_waves_per_eu(<min>[, <max>]))) - request minimum and/or maximum waves per execution unit Differential Revision: https://reviews.llvm.org/D24513 llvm-svn: 282371
2016-09-14CodeGen: simplify the logic a slight bitSaleem Abdulrasool1-4/+0
Move the definition of `getTriple()` into the header. It would just call `getTarget().getTriple()`. Inline the definition to allow the compiler to see the same amount of the layout as previously. Remove the more verbose `getTarget().getTriple()` in favour of `getTriple()`. llvm-svn: 281487
2016-09-07Fix whitespace issuesMatt Arsenault1-2/+1
^M and extra space llvm-svn: 280786
2016-08-30[PowerPC] Update the DWARF register-size tableHal Finkel1-3/+9
The PPC64 DWARF register-size table did not match the ABI specification (or GCC, for that matter). Fix that, and add a regression test. Fixes PR27931. llvm-svn: 280053
2016-08-25[MS] Win64 va_arg should expect large arguments to be passed indirectlyReid Kleckner1-1/+11
Fixes PR20569 llvm-svn: 279774
2016-08-22AMDGPU: Handle structs directly in AMDGPUABIInfoMatt Arsenault1-1/+41
Structs are currently handled as pointer + byval, which makes AMDGPU LLVM backend generate incorrect code when structs are used. This patch changes struct argument to be handled directly and without flattening, which Clover (Mesa 3D Gallium OpenCL state tracker) will be able to handle. Flattening would expand the struct to individual elements and pass each as a separate argument, which Clover can not handle. Furthermore, such expansion does not fit the OpenCL programming model which requires to explicitely specify each argument index, size and memory location. Patch by Vedran Miletić llvm-svn: 279463
2016-08-15[CodeGen] Ignore unnamed bitfields before handling vector fieldsDavid Majnemer1-4/+5
We processed unnamed bitfields after our logic for non-vector field elements in records larger than 128 bits. The vector logic would determine that the bit-field disqualifies the record from occupying a register despite the unnamed bit-field not participating in the record size nor its alignment. N.B. This behavior matches GCC and ICC. llvm-svn: 278656
2016-08-15[CodeGen] Correctly implement the AVX512 psABI rulesDavid Majnemer1-7/+10
An __m512 vector type wrapped in a structure should be passed in a vector register. Our prior implementation was based on a draft version of the psABI. This fixes PR28975. N.B. The update to the ABI was made here: https://github.com/hjl-tools/x86-psABI/commit/30f9c9 llvm-svn: 278655
2016-08-08Revert "[Attr] Add support for the `ms_hook_prologue` attribute."Charles Davis1-8/+0
This reverts commit r278050. It depends on r278048, which will be reverted. llvm-svn: 278052
2016-08-08[Attr] Add support for the `ms_hook_prologue` attribute.Charles Davis1-0/+8
Summary: Based on a patch by Michael Mueller. This attribute specifies that a function can be hooked or patched. This mechanism was originally devised by Microsoft for hotpatching their binaries (which they're constantly updating to stay ahead of crackers, script kiddies, and other ne'er-do-wells on the Internet), but it's now commonly abused by Windows programs that want to hook API functions. It is for this reason that this attribute was added to GCC--hence the name, `ms_hook_prologue`. Depends on D19908. Reviewers: rnk, aaron.ballman Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D19909 llvm-svn: 278050
2016-08-03[OpenCL] Fix size of image typeYaxun Liu1-9/+0
The size of image type is reported incorrectly as size of a pointer to address space 0, which causes error when casting image type to pointers by __builtin_astype. The fix is to get image address space from TargetInfo then report the size accordingly. Differential Revision: https://reviews.llvm.org/D22927 llvm-svn: 277647
2016-07-27Adjust coercion of aggregates on RenderScriptPirama Arumuga Nainar1-0/+46
Summary: In RenderScript, the size of the argument or return value emitted in the IR is expected to be the same as the size of corresponding qualified type. For ARM and AArch64, the coercion performed by Clang can change the parameter or return value to a type whose size is different (usually larger) than the original aggregate type. Specifically, this can happen in the following cases: - Aggregate parameters of size <= 64 bytes and return values smaller than 4 bytes on ARM - Aggregate parameters and return values smaller than bytes on AArch64 This patch coerces the cases above to an integer array that is the same size and alignment as the original aggregate. A new field is added to TargetInfo to detect a RenderScript target and limit this coercion just to that case. Tests added to test/CodeGen/renderscript.c Reviewers: rsmith Subscribers: aemerson, srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D22822 llvm-svn: 276904
2016-07-20[OpenCL] AMDGCN target will generate images in constant address spaceYaxun Liu1-0/+10
Allows AMDGCN target to generate images (such as %opencl.image2d_t) in constant address space. Images will still be generated in global address space by default. Added tests to existing opencl-types.cl in test\CodeGenOpenCL. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22523 llvm-svn: 276161
2016-07-19[OpenCL] Fixes bug of missing OCL version metadata on the AMDGCN targetYaxun Liu1-1/+12
Added the opencl.ocl.version metadata to be emitted with amdgcn. Created a static function emitOCLVerMD which is shared between triple spir and target amdgcn. Also added new testcases to existing test file, spir_version.cl inside test/CodeGenOpenCL. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22424 llvm-svn: 276010
2016-07-02Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer1-3/+2
where possible. No functionality change intended llvm-svn: 274432
2016-06-30AMDGPU: Set amdgpu_kernel calling convention for OpenCL kernels.Nikolay Haustov1-0/+13
Summary: Summary: Change Clang calling convention SpirKernel to OpenCLKernel. Set calling convention OpenCLKernel for amdgcn as well. Add virtual method .getOpenCLKernelCallingConv() to TargetCodeGenInfo and use it to set target calling convention for AMDGPU and SPIR. Update tests. Reviewers: rsmith, tstellarAMD, Anastasia, yaxunl Subscribers: kzhuravl, cfe-commits Differential Revision: http://reviews.llvm.org/D21367 llvm-svn: 274220
2016-06-24Add support for musl-libc on ARM Linux.Rafael Espindola1-0/+4
Patch by Lei Zhang! llvm-svn: 273735
2016-06-24This patch fixes problem with passing structures and unionsStrahinja Petrovic1-1/+2
smaller than register as argument in variadic functions on big endian architectures. Differential Revision: http://reviews.llvm.org/D21611 llvm-svn: 273665
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