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19 hours.users/MaskRay/spr/elf-add-print-gc-sectionsfileFangrui Song2-0/+5
19 hours[𝘀𝗽𝗿] initial versionFangrui Song5-8/+30
21 hours[RISCV] Use Subtarget member variable instead of getting it from MachineFunct...Craig Topper1-9/+7
21 hours[RISCV] Ignore debug instructions in RISCVVLOptimizer (#159616)Luke Lau2-1/+10
21 hours[libc++] Improve error resilience when running historical benchmarksLouis Dionne2-5/+2
21 hoursRevert "[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embe...Florian Mayer8-2462/+38
21 hoursTableGen: Replace assertion with error for unexpected pattern inputs (#159687)Matt Arsenault2-1/+30
22 hoursTableGen: Remove dead def of implicit node (#159688)Matt Arsenault1-1/+0
22 hours[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embed in Mem...Hank Chang8-38/+2462
22 hours[RISC-V] Add P-ext MC Support for Remaining Pair Operations (#159247)Qihan Cai3-2/+599
22 hours[C++20][Modules] Fix merging of anonymous members of class templates. (#155948)Michael Park5-1/+126
23 hours[bazel][mlir] Port #158722: complex.powi op (#159691)Jordan Rupprecht1-0/+2
23 hours[MLIR][Python] add type hints for accessors (#158455)Maksim Levental5-89/+471
23 hours[MLIR][Python] Add python bindings for IRDL dialect (#158488)Twice8-6/+236
23 hours[bazel][mlir] Port #158084: xegpu vectorlinearize pass (#159690)Jordan Rupprecht1-0/+1
24 hours[MLIR] Add new complex.powi op (#158722)Akash Banerjee16-120/+270
24 hours[LoongArch] Add generation support for `[x]vnori.b` (#158772)ZhaoQi4-6/+8
24 hours[IntrinsicEmitter] Make AttributesMap PackedID type-adaptive (#158383)Elvin Wang2-23/+34
24 hours[InferAddressSpaces] Extend undef pointer operand support to phi inst (#159548)Wenju He2-61/+76
24 hoursAMDGPU: Remove unnecessary AGPR legalize logic (#159491)Matt Arsenault1-13/+0
25 hours[Flang] Add new ConvertComplexPow pass for Flang (#158642)Akash Banerjee19-41/+307
25 hours[mlir][spirv] Simplify inheriting constructor declarations. NFC. (#159681)Jakub Kuderski17-111/+111
25 hoursGreedy: Take copy hints involving subregisters (#159570)Matt Arsenault9-89/+89
25 hoursAMDGPU: Add more mfma loop test cases (#159492)Matt Arsenault1-0/+517
25 hours[RISCV] Use bseti 31 for (or X, -2147483648) when upper 32 bits aren't used. ...Craig Topper2-1/+68
25 hours[RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147)Sam Elliott11-221/+1959
25 hours[mlir][vector] Fix crash in vector.from_elements folding with poison values ...Jhalak Patel2-19/+67
25 hoursFix libFuzzer array alignment with empty modules (#159661)Bitshift3-0/+70
25 hours[webkit.UncountedLambdaCapturesChecker] Treat arguments of std::ranges::all_o...Ryosuke Niwa2-30/+69
25 hours[scudo] Add missing tracing.h include to primary32 (#159668)Christopher Ferris2-0/+3
26 hours[AMDGPU] gfx1251 VOP3 dpp support (#159654)Stanislav Mekhanoshin13-53/+745
27 hours[clang][Dependency Scanning] Canonicalize Defines of a Compiler Invocation As...Qiongsi Wu2-2/+9
27 hours[lldb] Fix build when LLDB_ENABLE_PYTHON is OFF (#159665)Jonas Devlieghere1-0/+4
27 hours[AMDGPU] gfx1251 VOP2 dpp support (#159641)Stanislav Mekhanoshin5-35/+267
27 hours[PowerPC] fix float ABI selection on ppcle (#154773)DanilaZhebryakov2-1/+5
27 hours[mlir][XeGPU][Transform] Add vectorlinearize transform pass. (#158084)Md Abdullah Shahneous Bari4-0/+384
27 hours[RISCV] Pass SDValue by value. NFCCraig Topper1-4/+4
27 hours[LV] Always add uniform pointers to uniforms list.Florian Hahn2-20/+9
27 hours[libc++] Add a tool to produce historical libc++ benchmark resultsLouis Dionne2-12/+114
27 hours[llvm][clang] Pass VFS to `llvm::cl` command line handling (#159174)Jan Svoboda12-39/+54
27 hoursRevert "[mlir][SCF] Allow using a custom operation to generate loops with `ml...MaheshRavishankar5-659/+210
28 hours[lldb-dap] Bump form-data from 4.0.1 to 4.0.4Jonas Devlieghere1-15/+50
28 hours[HLSL] Make sure global resources and resource arrays cannot be assigned to (...Helena Kotas6-3/+70
28 hours[mlir][spirv] Use `verifySymbolUses` for `spirv.FunctionCall`. (#159399)Erick Ochoa Lopez3-9/+44
28 hours[SFrames] reland Emit and relax FREs #158154 (#159643)Sterling-Augustine13-85/+512
28 hours[libc][bazel] Add Bazel rules for rand/srand functions. (#159617)Alexey Samsonov2-0/+52
29 hours[lldb][NFC] Simplify logic in ABIMacOSX_arm64::FixDataAddress (#159612)Felipe de Azevedo Piovezan1-30/+27
29 hours[AMDGPU] gfx1251 VOP1 dpp support (#159637)Stanislav Mekhanoshin8-23/+379
29 hoursRISCV enable assembly unwinding (#158161)barsolo20005-13/+364
29 hours[RISCV] Update the vector integer division cycle in SiFive7 scheduling model ...Min-Yih Hsu14-177/+180
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