diff options
Diffstat (limited to 'llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp')
| -rw-r--r-- | llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp | 42 |
1 files changed, 34 insertions, 8 deletions
diff --git a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp index 56da4ce..00c9593 100644 --- a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp +++ b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp @@ -25,11 +25,24 @@ TEST(AMDGPU, TestWave64DwarfRegMapping) { // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95, // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815, // A0 => 3072, A255 => 3327 - for (int llvmReg : + for (int DwarfEncoding : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) { - MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true)); + MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false)); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true)); + } + + // We should get the correct LLVM register when round tripping through + // the dwarf encoding. + for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) { + int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false); + EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false)); + } + + // Verify that subregisters have no dwarf encoding. + for (MCRegister LLSubReg : + {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) { + EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1); } } } @@ -49,11 +62,24 @@ TEST(AMDGPU, TestWave32DwarfRegMapping) { // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95, // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791, // A0 => 2048, A255 => 2303 - for (int llvmReg : + for (int DwarfEncoding : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) { - MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true)); + MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false)); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true)); + } + + // We should get the correct LLVM register when round tripping through + // the dwarf encoding. + for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) { + int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false); + EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false)); + } + + // Verify that subregisters have no dwarf encoding. + for (MCRegister LLSubReg : + {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) { + EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1); } } } |