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-rw-r--r--llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp29
-rw-r--r--llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h23
2 files changed, 27 insertions, 25 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 3e1b058..37bf2d2 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -897,7 +897,7 @@ unsigned ComponentInfo::getIndexInParsedOperands(unsigned CompOprIdx) const {
}
std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
- std::function<unsigned(unsigned, unsigned)> GetRegIdx,
+ std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
const MCRegisterInfo &MRI, bool SkipSrc, bool AllowSameVGPR,
bool VOPD3) const {
@@ -914,12 +914,13 @@ std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
BaseX = X;
if (!BaseY)
BaseY = Y;
- if ((BaseX & BanksMask) == (BaseY & BanksMask))
+ if ((BaseX.id() & BanksMask) == (BaseY.id() & BanksMask))
return true;
if (BaseX != X /* This is 64-bit register */ &&
- ((BaseX + 1) & BanksMask) == (BaseY & BanksMask))
+ ((BaseX.id() + 1) & BanksMask) == (BaseY.id() & BanksMask))
return true;
- if (BaseY != Y && (BaseX & BanksMask) == ((BaseY + 1) & BanksMask))
+ if (BaseY != Y &&
+ (BaseX.id() & BanksMask) == ((BaseY.id() + 1) & BanksMask))
return true;
// If both are 64-bit bank conflict will be detected yet while checking
@@ -968,7 +969,7 @@ std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
// if the operand is not a register or not a VGPR.
InstInfo::RegIndices
InstInfo::getRegIndices(unsigned CompIdx,
- std::function<unsigned(unsigned, unsigned)> GetRegIdx,
+ std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
bool VOPD3) const {
assert(CompIdx < COMPONENTS_NUM);
@@ -983,7 +984,7 @@ InstInfo::getRegIndices(unsigned CompIdx,
Comp.hasRegSrcOperand(CompSrcIdx)
? GetRegIdx(CompIdx,
Comp.getIndexOfSrcInMCOperands(CompSrcIdx, VOPD3))
- : 0;
+ : MCRegister();
}
return RegIndices;
}
@@ -2697,8 +2698,8 @@ MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI) {
MCRegister mc2PseudoReg(MCRegister Reg) { MAP_REG2REG }
-bool isInlineValue(unsigned Reg) {
- switch (Reg) {
+bool isInlineValue(MCRegister Reg) {
+ switch (Reg.id()) {
case AMDGPU::SRC_SHARED_BASE_LO:
case AMDGPU::SRC_SHARED_BASE:
case AMDGPU::SRC_SHARED_LIMIT_LO:
@@ -3361,7 +3362,7 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
: getGfx9BufferFormatInfo(Format);
}
-const MCRegisterClass *getVGPRPhysRegClass(MCPhysReg Reg,
+const MCRegisterClass *getVGPRPhysRegClass(MCRegister Reg,
const MCRegisterInfo &MRI) {
const unsigned VGPRClasses[] = {
AMDGPU::VGPR_16RegClassID, AMDGPU::VGPR_32RegClassID,
@@ -3382,22 +3383,22 @@ const MCRegisterClass *getVGPRPhysRegClass(MCPhysReg Reg,
return nullptr;
}
-unsigned getVGPREncodingMSBs(MCPhysReg Reg, const MCRegisterInfo &MRI) {
+unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI) {
unsigned Enc = MRI.getEncodingValue(Reg);
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
return Idx >> 8;
}
-MCPhysReg getVGPRWithMSBs(MCPhysReg Reg, unsigned MSBs,
- const MCRegisterInfo &MRI) {
+MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs,
+ const MCRegisterInfo &MRI) {
unsigned Enc = MRI.getEncodingValue(Reg);
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
if (Idx >= 0x100)
- return AMDGPU::NoRegister;
+ return MCRegister();
const MCRegisterClass *RC = getVGPRPhysRegClass(Reg, MRI);
if (!RC)
- return AMDGPU::NoRegister;
+ return MCRegister();
Idx |= MSBs << 8;
if (RC->getID() == AMDGPU::VGPR_16RegClassID) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 5e3195b..9f65f93 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -909,7 +909,7 @@ private:
const ComponentInfo CompInfo[COMPONENTS_NUM];
public:
- using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
+ using RegIndices = std::array<MCRegister, Component::MAX_OPR_NUM>;
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
: CompInfo{OpX, OpY} {}
@@ -932,9 +932,10 @@ public:
// even though it violates requirement to be from different banks.
// If \p VOPD3 is set to true both dst registers allowed to be either odd
// or even and instruction may have real src2 as opposed to tied accumulator.
- bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
- const MCRegisterInfo &MRI, bool SkipSrc = false,
- bool AllowSameVGPR = false, bool VOPD3 = false) const {
+ bool
+ hasInvalidOperand(std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
+ const MCRegisterInfo &MRI, bool SkipSrc = false,
+ bool AllowSameVGPR = false, bool VOPD3 = false) const {
return getInvalidCompOperandIndex(GetRegIdx, MRI, SkipSrc, AllowSameVGPR,
VOPD3)
.has_value();
@@ -949,14 +950,14 @@ public:
// If \p VOPD3 is set to true both dst registers allowed to be either odd
// or even and instruction may have real src2 as opposed to tied accumulator.
std::optional<unsigned> getInvalidCompOperandIndex(
- std::function<unsigned(unsigned, unsigned)> GetRegIdx,
+ std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
const MCRegisterInfo &MRI, bool SkipSrc = false,
bool AllowSameVGPR = false, bool VOPD3 = false) const;
private:
RegIndices
getRegIndices(unsigned ComponentIdx,
- std::function<unsigned(unsigned, unsigned)> GetRegIdx,
+ std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
bool VOPD3) const;
};
@@ -1599,7 +1600,7 @@ LLVM_READNONE
MCRegister mc2PseudoReg(MCRegister Reg);
LLVM_READNONE
-bool isInlineValue(unsigned Reg);
+bool isInlineValue(MCRegister Reg);
/// Is this an AMDGPU specific source operand? These include registers,
/// inline constants, literals and mandatory literals (KImm).
@@ -1798,16 +1799,16 @@ bool isIntrinsicAlwaysUniform(unsigned IntrID);
/// \returns a register class for the physical register \p Reg if it is a VGPR
/// or nullptr otherwise.
-const MCRegisterClass *getVGPRPhysRegClass(MCPhysReg Reg,
+const MCRegisterClass *getVGPRPhysRegClass(MCRegister Reg,
const MCRegisterInfo &MRI);
/// \returns the MODE bits which have to be set by the S_SET_VGPR_MSB for the
/// physical register \p Reg.
-unsigned getVGPREncodingMSBs(MCPhysReg Reg, const MCRegisterInfo &MRI);
+unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI);
/// If \p Reg is a low VGPR return a corresponding high VGPR with \p MSBs set.
-MCPhysReg getVGPRWithMSBs(MCPhysReg Reg, unsigned MSBs,
- const MCRegisterInfo &MRI);
+MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs,
+ const MCRegisterInfo &MRI);
// Returns a table for the opcode with a given \p Desc to map the VGPR MSB
// set by the S_SET_VGPR_MSB to one of 4 sources. In case of VOPD returns 2
generated by cgit v1.1 at 2025-11-12 12:52:20 +0000