diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/TargetLowering.h | 1 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.h | 1 |
4 files changed, 16 insertions, 9 deletions
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index efa9887..191f4cc 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -4344,6 +4344,7 @@ public: /// bitwise ops etc. virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, + const APInt &DoNotPoisonEltMask, SelectionDAG &DAG, unsigned Depth) const; /// Return true if this function can prove that \p Op is never poison diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 6b5feef..931154b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -978,7 +978,7 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits( if (Op.getOpcode() >= ISD::BUILTIN_OP_END) if (SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode( - Op, DemandedBits, DemandedElts | DoNotPoisonEltMask, DAG, Depth)) + Op, DemandedBits, DemandedElts, DoNotPoisonEltMask, DAG, Depth)) return V; break; } @@ -4055,12 +4055,14 @@ bool TargetLowering::SimplifyDemandedBitsForTargetNode( Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use SimplifyDemandedBits if you don't know whether Op" " is a target node!"); - computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth); + computeKnownBitsForTargetNode(Op, Known, DemandedElts, + TLO.DAG, Depth); return false; } SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, + const APInt &DoNotPoisonEltMask, SelectionDAG &DAG, unsigned Depth) const { assert( (Op.getOpcode() >= ISD::BUILTIN_OP_END || diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 61ad2b8..528e752 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -44959,6 +44959,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode( SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, + const APInt &DoNotPoisonEltMask, SelectionDAG &DAG, unsigned Depth) const { int NumElts = DemandedElts.getBitWidth(); unsigned Opc = Op.getOpcode(); @@ -44972,7 +44973,8 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); MVT VecVT = Vec.getSimpleValueType(); if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && - !DemandedElts[CIdx->getZExtValue()]) + !DemandedElts[CIdx->getZExtValue()] && + !DoNotPoisonEltMask[CIdx->getZExtValue()]) return Vec; break; } @@ -45007,7 +45009,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( SDValue LHS = Op.getOperand(1); SDValue RHS = Op.getOperand(2); - KnownBits CondKnown = DAG.computeKnownBits(Cond, DemandedElts, Depth + 1); + KnownBits CondKnown = DAG.computeKnownBits(Cond, DemandedElts | DoNotPoisonEltMask, Depth + 1); if (CondKnown.isNegative()) return LHS; if (CondKnown.isNonNegative()) @@ -45019,8 +45021,8 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); - KnownBits LHSKnown = DAG.computeKnownBits(LHS, DemandedElts, Depth + 1); - KnownBits RHSKnown = DAG.computeKnownBits(RHS, DemandedElts, Depth + 1); + KnownBits LHSKnown = DAG.computeKnownBits(LHS, DemandedElts | DoNotPoisonEltMask, Depth + 1); + KnownBits RHSKnown = DAG.computeKnownBits(RHS, DemandedElts | DoNotPoisonEltMask, Depth + 1); // If all of the demanded bits are known 0 on LHS and known 0 on RHS, then // the (inverted) LHS bits cannot contribute to the result of the 'andn' in @@ -45034,7 +45036,8 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( APInt ShuffleUndef, ShuffleZero; SmallVector<int, 16> ShuffleMask; SmallVector<SDValue, 2> ShuffleOps; - if (getTargetShuffleInputs(Op, DemandedElts, ShuffleOps, ShuffleMask, + if (getTargetShuffleInputs(Op, DemandedElts | DoNotPoisonEltMask, + ShuffleOps, ShuffleMask, ShuffleUndef, ShuffleZero, DAG, Depth, false)) { // If all the demanded elts are from one operand and are inline, // then we can use the operand directly. @@ -45053,7 +45056,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( APInt IdentityOp = APInt::getAllOnes(NumOps); for (int i = 0; i != NumElts; ++i) { int M = ShuffleMask[i]; - if (!DemandedElts[i] || ShuffleUndef[i]) + if (!(DemandedElts[i] || DoNotPoisonEltMask[i]) || ShuffleUndef[i]) continue; int OpIdx = M / NumElts; int EltIdx = M % NumElts; @@ -45074,7 +45077,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( } return TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode( - Op, DemandedBits, DemandedElts, DAG, Depth); + Op, DemandedBits, DemandedElts, DoNotPoisonEltMask, DAG, Depth); } bool X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode( diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index dc32ec7..81a6e48 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1322,6 +1322,7 @@ namespace llvm { SDValue SimplifyMultipleUseDemandedBitsForTargetNode( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, + const APInt &DoNotPoisonEltMask, SelectionDAG &DAG, unsigned Depth) const override; bool isGuaranteedNotToBeUndefOrPoisonForTargetNode( |