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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-09 18:31:57 +0900 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-09 18:33:27 +0900 |
| commit | df025ebf872052c0761d44a3ef9b65e9675af8a8 (patch) | |
| tree | 9b4e94583e2536546d6606270bcdf846c95e1ba2 /llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp | |
| parent | 4428c9d0b1344179f85a72e183a44796976521e3 (diff) | |
| parent | bdcf47e4bcb92889665825654bb80a8bbe30379e (diff) | |
| download | llvm-users/chapuni/cov/single/loop.zip llvm-users/chapuni/cov/single/loop.tar.gz llvm-users/chapuni/cov/single/loop.tar.bz2 | |
Merge branch 'users/chapuni/cov/single/base' into users/chapuni/cov/single/loopusers/chapuni/cov/single/loop
Conflicts:
clang/lib/CodeGen/CoverageMappingGen.cpp
Diffstat (limited to 'llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp')
| -rw-r--r-- | llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp index a0c8437..259d68e 100644 --- a/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp +++ b/llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp @@ -51,10 +51,11 @@ TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) { // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95, // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815, // A0 => 3072, A255 => 3327 - for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) { - MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true)); + for (int DwarfEncoding : + {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) { + MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false)); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true)); } } } @@ -70,10 +71,11 @@ TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) { // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95, // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791, // A0 => 2048, A255 => 2303 - for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) { - MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); - EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true)); + for (int DwarfEncoding : + {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) { + MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false)); + EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true)); } } } |