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authormingmingl <mingmingl@google.com>2025-02-04 11:11:14 -0800
committermingmingl <mingmingl@google.com>2025-02-04 11:11:14 -0800
commite91747a92d27ecf799427bf563f9f64f7c4d2447 (patch)
tree7aa5a8a9170deec293e152bdf2be804399dcd612 /llvm/lib/TargetParser/ARMTargetParser.cpp
parent3a8d9337d816aef41c3ca1484be8b933a71a3c46 (diff)
parent53d6e59b594639417cdbfcfa2d18cea64acb4009 (diff)
downloadllvm-users/mingmingl-llvm/spr/sdpglobalvariable.zip
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Merge branch 'main' into users/mingmingl-llvm/spr/sdpglobalvariableusers/mingmingl-llvm/spr/sdpglobalvariable
Diffstat (limited to 'llvm/lib/TargetParser/ARMTargetParser.cpp')
-rw-r--r--llvm/lib/TargetParser/ARMTargetParser.cpp9
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 9bcfa6c..8f97537 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -403,13 +403,12 @@ static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind InputFPUKind) {
if (!ARM::isDoublePrecision(InputFPU.Restriction))
return InputFPUKind;
- // Otherwise, look for an FPU entry with all the same fields, except
- // that it does not support double precision.
+ // Otherwise, look for an FPU entry that has the same FPUVer
+ // and is not Double Precision. We want to allow for changing of
+ // NEON Support and Restrictions so CPU's such as Cortex-R52 can
+ // select between SP Only and Full DP modes.
for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
- CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
- ARM::has32Regs(CandidateFPU.Restriction) ==
- ARM::has32Regs(InputFPU.Restriction) &&
!ARM::isDoublePrecision(CandidateFPU.Restriction)) {
return CandidateFPU.ID;
}