[AArch64][ISel] Subvector extracts can use undef for second EXT inputusers/gbossu.vector.extract.1

This will later allow us to use the SVE2 constructive variant of EXT
without requiring a MOV. That is because that variant of EXT requires
two consecutive Z registers as input. As a consequence, extracting a
subvector from e.g. z2 into z0 would require:
  z3 = MOV z2
  z0 = EXT_ZZI_B { z2, z3 }, idx

With this change, the z3 part of the { z2, z3 } tuple will be marked as
undef, allowing the MOV to be simplified.

We just need to add patterns for EXT_ZZI_B now, currently only the the
destructive EXT_ZZI variant is selected.

1 files changed, 3 insertions, 1 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 7c9fc67..16f0229 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15544,7 +15544,9 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
 
     assert(InVT.isScalableVector() && "Unexpected vector type!");
     // Move requested subvector to the start of the vector and try again.
-    SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, Vec, Idx);
+    // There's no need for a second input to vector_splice, so use undef there.
+    SDValue Splice =
+        DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, DAG.getUNDEF(InVT), Idx);
     return convertFromScalableVector(DAG, VT, Splice);
   }