aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
diff options
context:
space:
mode:
authorNAKAMURA Takumi <geek4civic@gmail.com>2025-01-09 18:43:11 +0900
committerNAKAMURA Takumi <geek4civic@gmail.com>2025-01-09 18:43:11 +0900
commit0e1a753549b29ff1f5a190aca83b803a33b51628 (patch)
treee5578f8810c65711304128d0c8add7fa1f77b9d8 /llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
parent3c6252260ee11e3a453076b4d96ffffe20d49998 (diff)
parentbdcf47e4bcb92889665825654bb80a8bbe30379e (diff)
downloadllvm-users/chapuni/cov/single/if.zip
llvm-users/chapuni/cov/single/if.tar.gz
llvm-users/chapuni/cov/single/if.tar.bz2
Merge branch 'users/chapuni/cov/single/base' into users/chapuni/cov/single/ifusers/chapuni/cov/single/if
Conflicts: clang/lib/CodeGen/CoverageMappingGen.cpp
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp')
-rw-r--r--llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp24
1 files changed, 19 insertions, 5 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 49192bd..850d624 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1663,7 +1663,7 @@ InstructionCost RISCVTTIImpl::getStoreImmCost(Type *Ty,
return 0;
if (OpInfo.isUniform())
- // vmv.x.i, vmv.v.x, or vfmv.v.f
+ // vmv.v.i, vmv.v.x, or vfmv.v.f
// We ignore the cost of the scalar constant materialization to be consistent
// with how we treat scalar constants themselves just above.
return 1;
@@ -2329,6 +2329,15 @@ unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth);
}
+TTI::AddressingModeKind
+RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
+ ScalarEvolution *SE) const {
+ if (ST->hasVendorXCVmem() && !ST->is64Bit())
+ return TTI::AMK_PostIndexed;
+
+ return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
+}
+
bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
const TargetTransformInfo::LSRCost &C2) {
// RISC-V specific here are "instruction number 1st priority".
@@ -2549,16 +2558,21 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
TTI::MemCmpExpansionOptions Options;
// TODO: Enable expansion when unaligned access is not supported after we fix
// issues in ExpandMemcmp.
- if (!(ST->enableUnalignedScalarMem() &&
- (ST->hasStdExtZbb() || ST->hasStdExtZbkb() || IsZeroCmp)))
+ if (!ST->enableUnalignedScalarMem())
+ return Options;
+
+ if (!ST->hasStdExtZbb() && !ST->hasStdExtZbkb() && !IsZeroCmp)
return Options;
Options.AllowOverlappingLoads = true;
Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
Options.NumLoadsPerBlock = Options.MaxNumLoads;
- if (ST->is64Bit())
+ if (ST->is64Bit()) {
Options.LoadSizes = {8, 4, 2, 1};
- else
+ Options.AllowedTailExpansions = {3, 5, 6};
+ } else {
Options.LoadSizes = {4, 2, 1};
+ Options.AllowedTailExpansions = {3};
+ }
return Options;
}