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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-10 19:25:56 +0900 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-10 19:25:56 +0900 |
| commit | 63f5dc16d6bfca0512fb034052b41d13c3751e20 (patch) | |
| tree | e70266be1fda941e0974e71e3d2c1cf080081311 /llvm/lib/Target/RISCV/RISCVISelLowering.cpp | |
| parent | 9e5734688ed3d5f6b3fb76a26b3d90a736d60781 (diff) | |
| parent | 397ac44f623f891d8f05d6673a95984ac0a26671 (diff) | |
| download | llvm-users/chapuni/cov/single/unify.zip llvm-users/chapuni/cov/single/unify.tar.gz llvm-users/chapuni/cov/single/unify.tar.bz2 | |
Merge branch 'main' into users/chapuni/cov/single/unifyusers/chapuni/cov/single/unify
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 4a0304f..6c58989 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -18385,7 +18385,7 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift( auto *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)); // Bail if we might break a sh{1,2,3}add pattern. - if (Subtarget.hasStdExtZba() && C2->getZExtValue() >= 1 && + if (Subtarget.hasStdExtZba() && C2 && C2->getZExtValue() >= 1 && C2->getZExtValue() <= 3 && N->hasOneUse() && N->user_begin()->getOpcode() == ISD::ADD && !isUsedByLdSt(*N->user_begin(), nullptr) && @@ -20273,13 +20273,11 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, for (auto &Reg : RegsToPass) Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); - if (!IsTailCall) { - // Add a register mask operand representing the call-preserved registers. - const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); - const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); - assert(Mask && "Missing call preserved mask for calling convention"); - Ops.push_back(DAG.getRegisterMask(Mask)); - } + // Add a register mask operand representing the call-preserved registers. + const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); + assert(Mask && "Missing call preserved mask for calling convention"); + Ops.push_back(DAG.getRegisterMask(Mask)); // Glue the call to the argument copies, if any. if (Glue.getNode()) |