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authorNadav Rotem <nadav.rotem@intel.com>2011-05-27 21:03:13 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-05-27 21:03:13 +0000
commita9effb13ddc7b008a99981b3639a65ec91a1a35c (patch)
tree246ee9bfbd4824473fe9543dfc3981a923fbec5a /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
parentd368a84c916c88c1874efff9800311717953fa7d (diff)
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Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
code in one place. Re-apply 131534 and fix the multi-step promotion of integers. llvm-svn: 132217
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a83bd4f..925bb26 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -892,7 +892,7 @@ unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
// If there is a wider vector type with the same element type as this one,
// we should widen to that legal vector type. This handles things like
// <2 x float> -> <4 x float>.
- if (NumElts != 1 && getTypeAction(VT) == Promote) {
+ if (NumElts != 1 && getTypeAction(Context, VT) == Promote) {
RegisterVT = getTypeToTransformTo(Context, VT);
if (isTypeLegal(RegisterVT)) {
IntermediateVT = RegisterVT;