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author | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-09 17:16:04 +0900 |
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committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-09 17:16:04 +0900 |
commit | 0aa930a41f2d1ebf1fa90ec42da8f96d15a4dcbb (patch) | |
tree | 6a77b463f700e090df586672c26b9fe765fd115b /llvm/lib/CodeGen/GlobalISel/Utils.cpp | |
parent | ec6892d1c979ce0b84c86918d5cdbb03037b409a (diff) | |
parent | 6d16b1c5c468a79ecf867293023c89ac518ecdda (diff) | |
download | llvm-users/chapuni/cov/single/nextcount-base.zip llvm-users/chapuni/cov/single/nextcount-base.tar.gz llvm-users/chapuni/cov/single/nextcount-base.tar.bz2 |
Merge branch 'users/chapuni/cov/single/pair' into users/chapuni/cov/single/nextcount-baseusers/chapuni/cov/single/nextcount-base
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/Utils.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/Utils.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index 8c1e41e..625d556 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -276,6 +276,21 @@ void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, reportGISelFailure(MF, TPC, MORE, R); } +unsigned llvm::getInverseGMinMaxOpcode(unsigned MinMaxOpc) { + switch (MinMaxOpc) { + case TargetOpcode::G_SMIN: + return TargetOpcode::G_SMAX; + case TargetOpcode::G_SMAX: + return TargetOpcode::G_SMIN; + case TargetOpcode::G_UMIN: + return TargetOpcode::G_UMAX; + case TargetOpcode::G_UMAX: + return TargetOpcode::G_UMIN; + default: + llvm_unreachable("unrecognized opcode"); + } +} + std::optional<APInt> llvm::getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI) { std::optional<ValueAndVReg> ValAndVReg = getIConstantVRegValWithLookThrough( @@ -1517,6 +1532,18 @@ llvm::isConstantOrConstantSplatVector(MachineInstr &MI, return APInt(ScalarSize, *MaybeCst, true); } +std::optional<APFloat> +llvm::isConstantOrConstantSplatVectorFP(MachineInstr &MI, + const MachineRegisterInfo &MRI) { + Register Def = MI.getOperand(0).getReg(); + if (auto FpConst = getFConstantVRegValWithLookThrough(Def, MRI)) + return FpConst->Value; + auto MaybeCstFP = getFConstantSplat(Def, MRI, /*allowUndef=*/false); + if (!MaybeCstFP) + return std::nullopt; + return MaybeCstFP->Value; +} + bool llvm::isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs) { switch (MI.getOpcode()) { |