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| author | Brendon Cahoon <brendon.cahoon@amd.com> | 2021-04-30 09:57:44 -0400 |
|---|---|---|
| committer | Brendon Cahoon <brendon.cahoon@amd.com> | 2021-06-28 09:06:44 -0400 |
| commit | f9f5d415453b3fee98817d4f0bd8e5b5415e34cc (patch) | |
| tree | 308b18955db615c2245484ee0f39394734ccf2b7 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 22aa3680eaccb9b77ca224711c4da3a354aa2d45 (diff) | |
| download | llvm-f9f5d415453b3fee98817d4f0bd8e5b5415e34cc.zip llvm-f9f5d415453b3fee98817d4f0bd8e5b5415e34cc.tar.gz llvm-f9f5d415453b3fee98817d4f0bd8e5b5415e34cc.tar.bz2 | |
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
Adds legalizer, register bank select, and instruction
select support for G_SBFX and G_UBFX. These opcodes generate
scalar or vector ALU bitfield extract instructions for
AMDGPU. The instructions allow both constant or register
values for the offset and width operands.
The 32-bit scalar version is expanded to a sequence that
combines the offset and width into a single register.
There are no 64-bit vgpr bitfield extract instructions, so the
operations are expanded to a sequence of instructions that
implement the operation. If the width is a constant,
then the 32-bit bitfield extract instructions are used.
Moved the AArch64 specific code for creating G_SBFX to
CombinerHelper.cpp so that it can be used by other targets.
Only bitfield extracts with constant offset and width values
are handled currently.
Differential Revision: https://reviews.llvm.org/D100149
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions