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| author | David Sherwood <david.sherwood@arm.com> | 2022-11-18 13:07:35 +0000 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2022-11-18 14:30:48 +0000 |
| commit | 2e02f007a27310abaea60f7749093c95e61c813a (patch) | |
| tree | 1b8712e10dd0459425dfd7060176783c41986af4 /lldb/source/Plugins/ScriptInterpreter/Python | |
| parent | bc270f9ed1c86db3f3a537dc6f91cda94737b915 (diff) | |
| download | llvm-2e02f007a27310abaea60f7749093c95e61c813a.zip llvm-2e02f007a27310abaea60f7749093c95e61c813a.tar.gz llvm-2e02f007a27310abaea60f7749093c95e61c813a.tar.bz2 | |
[AArch64][SME2] Remove vector constraints from zip/uzp (2-vector) instruction classes
The zip/uzp (2-vector) instruction classes have the incorrect
register constraints and mark the destination as also being an
input. However, the instructions are fully destructive so I've
restructured the classes.
Differential Revision: https://reviews.llvm.org/D138288
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python')
0 files changed, 0 insertions, 0 deletions