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| author | Austin Kerbow <Austin.Kerbow@amd.com> | 2020-11-05 23:43:58 -0800 |
|---|---|---|
| committer | Austin Kerbow <Austin.Kerbow@amd.com> | 2020-12-08 12:24:12 -0800 |
| commit | 4aa842a800b53806a9e25f03b4e21f6879801a38 (patch) | |
| tree | 92543d518e575ca4a2849e08d1d75309a6967e00 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 98bca0a60574c4276cfc85833fe29d8f4beff7f6 (diff) | |
| download | llvm-4aa842a800b53806a9e25f03b4e21f6879801a38.zip llvm-4aa842a800b53806a9e25f03b4e21f6879801a38.tar.gz llvm-4aa842a800b53806a9e25f03b4e21f6879801a38.tar.bz2 | |
[AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing
It is possible for copies or spills to be inserted in the middle of indirect
addressing sequences which use VGPR indexing. Spills to accvgprs could be
effected by the indexing mode.
Add new pseudo instructions that are expanded after register allocation to avoid
the problematic spill or copy placement.
Differential Revision: https://reviews.llvm.org/D91048
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions