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| author | Craig Topper <craig.topper@sifive.com> | 2022-01-18 11:42:25 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-01-18 11:47:50 -0800 |
| commit | 5a6c622afdff2c18d82dbe4f463450feaa8b7e5e (patch) | |
| tree | e0857d76fd4b0dde541489667c7fd26f2c2668af /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | 138cc5a0010d5c70eefe9204df8d79988d7aad32 (diff) | |
| download | llvm-5a6c622afdff2c18d82dbe4f463450feaa8b7e5e.zip llvm-5a6c622afdff2c18d82dbe4f463450feaa8b7e5e.tar.gz llvm-5a6c622afdff2c18d82dbe4f463450feaa8b7e5e.tar.bz2 | |
[RISCV] Remove special case for constant shift amount in FSHL/FSHR lowering to FSL/FSR.
Remove fshl/fshr with constant shift amount isel patterns. Replace
with fsr/fsl with constant isel patterns.
This hack was trying to preserve as much optimization opportunity
for fshl/fshr by constant as possible, but the conversion to
RISCVISD::FSR/FSL happens so late it probably isn't worth much.
The new isel patterns are needed by D117468 anyway.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
0 files changed, 0 insertions, 0 deletions