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| author | Emmmer <yjhdandan@163.com> | 2022-08-10 21:36:48 +0800 |
|---|---|---|
| committer | Emmmer <yjhdandan@163.com> | 2022-08-11 14:26:22 +0800 |
| commit | 0247b5aaae7ae02f140ca9509dc68078cfe55898 (patch) | |
| tree | 27f0d225e9b42652c4cd95de0cc40fe8c69a6394 /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h | |
| parent | bcc90f6268182a42205bd546be996fac6d05a071 (diff) | |
| download | llvm-0247b5aaae7ae02f140ca9509dc68078cfe55898.zip llvm-0247b5aaae7ae02f140ca9509dc68078cfe55898.tar.gz llvm-0247b5aaae7ae02f140ca9509dc68078cfe55898.tar.bz2 | |
[LLDB][RISCV] Add riscv software breakpoint trap code
Added:
- Take RISC-V `ebreak` instruction as breakpoint trap code, so our breakpoint works as expected now.
Further work:
- RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
- Add support for RVC extension (the trap code, etc.).
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D131566
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h')
0 files changed, 0 insertions, 0 deletions