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authorChad Rosier <mcrosier@apple.com>2011-12-15 22:11:31 +0000
committerChad Rosier <mcrosier@apple.com>2011-12-15 22:11:31 +0000
commit41dbf59e12ef3aa5c5694e137b200acbd3d0df20 (patch)
tree840d710b9487e320d5dc8b6afab10ccb6606e905
parentcd1aba8b4dba01c15b90bd0a2a99750140e627e6 (diff)
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Add missing zmovl AVX patterns which were causing crashes.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! llvm-svn: 146689
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td6
-rw-r--r--llvm/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll8
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 24e7ee4..8c16fe5 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -618,6 +618,9 @@ let Predicates = [HasAVX] in {
(SUBREG_TO_REG (i64 0),
(v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
sub_xmm)>;
+ def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
+ (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
+ (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
// Move low f64 and clear high bits.
def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
@@ -800,6 +803,9 @@ let Predicates = [HasAVX] in {
def : Pat<(v8i32 (X86vzmovl
(insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
+def : Pat<(v4i64 (X86vzmovl
+ (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
+ (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
def : Pat<(v8f32 (X86vzmovl
(insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
diff --git a/llvm/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll b/llvm/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
index 26670c1..d9781027 100644
--- a/llvm/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
+++ b/llvm/test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
@@ -61,3 +61,11 @@ t2.exit: ; preds = %0, %loop
return: ; preds = %loop.cond
ret void
}
+
+define <3 x i64> @t4() nounwind {
+entry:
+ %0 = load <2 x i64> addrspace(1)* undef, align 16
+ %1 = extractelement <2 x i64> %0, i32 0
+ %2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 0
+ ret <3 x i64> %2
+}