diff options
| author | Qi Zhao <zhaoqi01@loongson.cn> | 2025-08-11 14:08:31 +0800 |
|---|---|---|
| committer | Qi Zhao <zhaoqi01@loongson.cn> | 2025-08-11 14:08:31 +0800 |
| commit | ef4d37b370a1cd42927ddbd385a70a50e67980a6 (patch) | |
| tree | 8ae124bd45f15b5b3efae977c337aa24269e6e1e | |
| parent | 47ba25174180491a40372a8d3fc4f7ed49a8f5f6 (diff) | |
| download | llvm-users/zhaoqi5/vec-legaladdressingmode.zip llvm-users/zhaoqi5/vec-legaladdressingmode.tar.gz llvm-users/zhaoqi5/vec-legaladdressingmode.tar.bz2 | |
only isint12users/zhaoqi5/vec-legaladdressingmode
| -rw-r--r-- | llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index f6e6dfe..5afdc34 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -8403,15 +8403,6 @@ bool LoongArchTargetLowering::isLegalAddressingMode(const DataLayout &DL, Subtarget.hasUAL() && !isa<VectorType>(Ty))) return false; - // FIXME: Is it necessary and possible to perform fine-grained processing - // according to vector element types? - if (Subtarget.hasExtLSX() && isa<VectorType>(Ty) && - !(isInt<8>(AM.BaseOffs) || isShiftedInt<8, 1>(AM.BaseOffs) || - isShiftedInt<8, 2>(AM.BaseOffs) || isShiftedInt<8, 3>(AM.BaseOffs) || - isShiftedInt<11, 1>(AM.BaseOffs) || isShiftedInt<10, 2>(AM.BaseOffs) || - isShiftedInt<9, 3>(AM.BaseOffs))) - return false; - switch (AM.Scale) { case 0: // "r+i" or just "i", depending on HasBaseReg. |