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author | Vitaly Buka <vitalybuka@google.com> | 2024-10-11 17:29:10 -0700 |
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committer | Vitaly Buka <vitalybuka@google.com> | 2024-10-11 17:29:10 -0700 |
commit | 62a5908eed6487f7da088fec7630c9d54fd4a797 (patch) | |
tree | 818af6c78b73d897717c709b2c928b42f48b3b66 | |
parent | ff5148a21cc61491ddb3db1ff38aafc8614b99bc (diff) | |
parent | aa44f59abf399f81585898fb95e66518ef3591af (diff) | |
download | llvm-users/vitalybuka/spr/main.lsan-log-thread-history.zip llvm-users/vitalybuka/spr/main.lsan-log-thread-history.tar.gz llvm-users/vitalybuka/spr/main.lsan-log-thread-history.tar.bz2 |
[𝘀𝗽𝗿] changes introduced through rebaseusers/vitalybuka/spr/main.lsan-log-thread-history
Created using spr 1.3.4
[skip ci]
-rw-r--r-- | compiler-rt/lib/lsan/lsan_common.cpp | 8 | ||||
-rw-r--r-- | compiler-rt/lib/lsan/lsan_flags.inc | 1 | ||||
-rw-r--r-- | compiler-rt/test/lsan/TestCases/flag_tries.c | 23 | ||||
-rw-r--r-- | libc/src/__support/str_to_integer.h | 17 | ||||
-rw-r--r-- | llvm/docs/Coroutines.rst | 2 | ||||
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rv32xtheadbb.ll | 31 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 62 |
8 files changed, 133 insertions, 14 deletions
diff --git a/compiler-rt/lib/lsan/lsan_common.cpp b/compiler-rt/lib/lsan/lsan_common.cpp index 6776598..52d0a8c3 100644 --- a/compiler-rt/lib/lsan/lsan_common.cpp +++ b/compiler-rt/lib/lsan/lsan_common.cpp @@ -778,7 +778,7 @@ static bool PrintResults(LeakReport &report) { return false; } -static bool CheckForLeaks() { +static bool CheckForLeaksOnce() { if (&__lsan_is_turned_off && __lsan_is_turned_off()) { VReport(1, "LeakSanitizer is disabled\n"); return false; @@ -830,6 +830,12 @@ static bool CheckForLeaks() { } } +static bool CheckForLeaks() { + int leaking_tries = 0; + for (int i = 0; i < flags()->tries; ++i) leaking_tries += CheckForLeaksOnce(); + return leaking_tries == flags()->tries; +} + static bool has_reported_leaks = false; bool HasReportedLeaks() { return has_reported_leaks; } diff --git a/compiler-rt/lib/lsan/lsan_flags.inc b/compiler-rt/lib/lsan/lsan_flags.inc index b7f2822..c97b021 100644 --- a/compiler-rt/lib/lsan/lsan_flags.inc +++ b/compiler-rt/lib/lsan/lsan_flags.inc @@ -43,6 +43,7 @@ LSAN_FLAG(bool, use_poisoned, false, "Consider pointers found in poisoned memory to be valid.") LSAN_FLAG(bool, log_pointers, false, "Debug logging") LSAN_FLAG(bool, log_threads, false, "Debug logging") +LSAN_FLAG(int, tries, 1, "Debug option to repeat leak checking multiple times") LSAN_FLAG(const char *, suppressions, "", "Suppressions file name.") LSAN_FLAG(int, thread_suspend_fail, 1, "Behaviour if thread suspendion all thread (0 - " diff --git a/compiler-rt/test/lsan/TestCases/flag_tries.c b/compiler-rt/test/lsan/TestCases/flag_tries.c new file mode 100644 index 0000000..d6af766 --- /dev/null +++ b/compiler-rt/test/lsan/TestCases/flag_tries.c @@ -0,0 +1,23 @@ +// Test retries option of lsan. +// RUN: %clang_lsan %s -o %t +// RUN: %env_lsan_opts=use_stacks=0:use_registers=0:symbolize=0 %run %t foo 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK1 +// RUN: %env_lsan_opts=use_stacks=0:use_registers=0:symbolize=0:tries=12 %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK12 + +#include <assert.h> +#include <sanitizer/lsan_interface.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +void *p; + +int main(int argc, char *argv[]) { + fprintf(stderr, "Test alloc: %p.\n", malloc(1337)); + // CHECK: Test alloc: + + assert(__lsan_do_recoverable_leak_check() == 1); + // CHECK1-COUNT-1: SUMMARY: {{.*}}Sanitizer: 1337 byte + // CHECK12-COUNT-12: SUMMARY: {{.*}}Sanitizer: 1337 byte + + _exit(0); +} diff --git a/libc/src/__support/str_to_integer.h b/libc/src/__support/str_to_integer.h index 1f80229..ea17178 100644 --- a/libc/src/__support/str_to_integer.h +++ b/libc/src/__support/str_to_integer.h @@ -11,6 +11,8 @@ #include "src/__support/CPP/limits.h" #include "src/__support/CPP/type_traits.h" +#include "src/__support/CPP/type_traits/make_unsigned.h" +#include "src/__support/big_int.h" #include "src/__support/common.h" #include "src/__support/ctype_utils.h" #include "src/__support/macros/config.h" @@ -77,9 +79,7 @@ template <class T> LIBC_INLINE StrToNumResult<T> strtointeger(const char *__restrict src, int base, const size_t src_len = cpp::numeric_limits<size_t>::max()) { - using ResultType = typename cpp::conditional_t<(cpp::is_same_v<T, UInt128> || - cpp::is_same_v<T, Int128>), - UInt128, unsigned long long>; + using ResultType = make_integral_or_big_int_unsigned_t<T>; ResultType result = 0; @@ -137,13 +137,13 @@ strtointeger(const char *__restrict src, int base, result = abs_max; error_val = ERANGE; } else { - result = result * base; + result = static_cast<ResultType>(result * base); } if (result > abs_max - cur_digit) { result = abs_max; error_val = ERANGE; } else { - result = result + cur_digit; + result = static_cast<ResultType>(result + cur_digit); } } @@ -156,12 +156,7 @@ strtointeger(const char *__restrict src, int base, return {cpp::numeric_limits<T>::min(), str_len, error_val}; } - return { - is_positive - ? static_cast<T>(result) - : static_cast<T>( - -static_cast<make_integral_or_big_int_unsigned_t<T>>(result)), - str_len, error_val}; + return {static_cast<T>(is_positive ? result : -result), str_len, error_val}; } } // namespace internal diff --git a/llvm/docs/Coroutines.rst b/llvm/docs/Coroutines.rst index 8794df6..92e138b 100644 --- a/llvm/docs/Coroutines.rst +++ b/llvm/docs/Coroutines.rst @@ -1090,7 +1090,7 @@ The first and second arguments are identical to those of the `coro.begin` intrinsic. The third argument is an i32 index of the generator list given to the -`CoroSplit` pass specifying the custom ABI generator lor this coroutine. +`CoroSplit` pass specifying the custom ABI generator for this coroutine. Semantics: """""""""" diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index e71c8c3..9fe989b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -299,7 +299,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction({ISD::VAARG, ISD::VACOPY, ISD::VAEND}, MVT::Other, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + if (!Subtarget.hasVendorXTHeadBb()) + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); diff --git a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll index 197366e..248d620 100644 --- a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll @@ -266,6 +266,37 @@ define i64 @cttz_i64(i64 %a) nounwind { ret i64 %1 } +define i32 @sexti1_i32(i32 %a) nounwind { +; RV32I-LABEL: sexti1_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a0, a0, 31 +; RV32I-NEXT: srai a0, a0, 31 +; RV32I-NEXT: ret +; +; RV32XTHEADBB-LABEL: sexti1_i32: +; RV32XTHEADBB: # %bb.0: +; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0 +; RV32XTHEADBB-NEXT: ret + %shl = shl i32 %a, 31 + %shr = ashr exact i32 %shl, 31 + ret i32 %shr +} + +define i32 @sexti1_i32_2(i1 %a) nounwind { +; RV32I-LABEL: sexti1_i32_2: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a0, a0, 31 +; RV32I-NEXT: srai a0, a0, 31 +; RV32I-NEXT: ret +; +; RV32XTHEADBB-LABEL: sexti1_i32_2: +; RV32XTHEADBB: # %bb.0: +; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0 +; RV32XTHEADBB-NEXT: ret + %sext = sext i1 %a to i32 + ret i32 %sext +} + define i32 @sextb_i32(i32 %a) nounwind { ; RV32I-LABEL: sextb_i32: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll index 8ce4c44..47c4e8b 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll @@ -558,6 +558,68 @@ define i64 @cttz_i64(i64 %a) nounwind { ret i64 %1 } +define signext i32 @sexti1_i32(i32 signext %a) nounwind { +; RV64I-LABEL: sexti1_i32: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 63 +; RV64I-NEXT: srai a0, a0, 63 +; RV64I-NEXT: ret +; +; RV64XTHEADBB-LABEL: sexti1_i32: +; RV64XTHEADBB: # %bb.0: +; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0 +; RV64XTHEADBB-NEXT: ret + %shl = shl i32 %a, 31 + %shr = ashr exact i32 %shl, 31 + ret i32 %shr +} + +define signext i32 @sexti1_i32_2(i1 %a) nounwind { +; RV64I-LABEL: sexti1_i32_2: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 63 +; RV64I-NEXT: srai a0, a0, 63 +; RV64I-NEXT: ret +; +; RV64XTHEADBB-LABEL: sexti1_i32_2: +; RV64XTHEADBB: # %bb.0: +; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0 +; RV64XTHEADBB-NEXT: ret + %sext = sext i1 %a to i32 + ret i32 %sext +} + +define i64 @sexti1_i64(i64 %a) nounwind { +; RV64I-LABEL: sexti1_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 63 +; RV64I-NEXT: srai a0, a0, 63 +; RV64I-NEXT: ret +; +; RV64XTHEADBB-LABEL: sexti1_i64: +; RV64XTHEADBB: # %bb.0: +; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0 +; RV64XTHEADBB-NEXT: ret + %shl = shl i64 %a, 63 + %shr = ashr exact i64 %shl, 63 + ret i64 %shr +} + +define i64 @sexti1_i64_2(i1 %a) nounwind { +; RV64I-LABEL: sexti1_i64_2: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 63 +; RV64I-NEXT: srai a0, a0, 63 +; RV64I-NEXT: ret +; +; RV64XTHEADBB-LABEL: sexti1_i64_2: +; RV64XTHEADBB: # %bb.0: +; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0 +; RV64XTHEADBB-NEXT: ret + %sext = sext i1 %a to i64 + ret i64 %sext +} + define signext i32 @sextb_i32(i32 signext %a) nounwind { ; RV64I-LABEL: sextb_i32: ; RV64I: # %bb.0: |