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authorRuiling Song <ruiling.song@amd.com>2026-02-11 10:59:09 +0800
committerRuiling Song <ruiling.song@amd.com>2026-02-11 10:59:09 +0800
commit50d65e841172b0d8e86bd976ff65d8bf80946920 (patch)
tree81c9097fb0e604c5f6d2645c60eb57cf3a416d1c
parent5ae2ee926d98b7fe902ad6d9ac95bb24231bc6a4 (diff)
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Update comment slightlyusers/ruiling/opt-global-addr
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp5
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp5
2 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index ff3eb0e1eee0..1064df8a9080 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -2053,8 +2053,9 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N, SDValue Addr,
if (TII->isLegalFLATOffset(COffset, AMDGPUAS::GLOBAL_ADDRESS,
SIInstrFlags::FlatGlobal)) {
// If the MSB of the first operand of the addition is known to be
- // zero, which is followed by zext, we are sure overflow would not
- // happen during addition.
+ // zero, which is followed by zext, this makes sure:
+ // a.) for unsigned VOffset, no overflow would happen.
+ // b.) for signed VOffset, the value can be properly encoded.
if (RHS.getOpcode() == ISD::ZERO_EXTEND &&
CurDAG->SignBitIsZero(ExtRHS.getOperand(0))) {
VOffset = ExtRHS.getOperand(0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 44eacf6e4ed4..0a29cdd4cbda 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -5856,8 +5856,9 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root,
AMDGPUAS::GLOBAL_ADDRESS,
SIInstrFlags::FlatGlobal)) {
// If the MSB of the first operand of the addition is known to be
- // zero, which is followed by zext, we are sure overflow would not
- // happen for the addition.
+ // zero, which is followed by zext, this makes sure:
+ // a.) for unsigned VOffset, no overflow would happen.
+ // b.) for signed VOffset, the value can be properly encoded.
if (matchZeroExtendFromS32OrS32(PtrBaseOffset) &&
VT->signBitIsZero(VOffsetDef->getOperand(1).getReg())) {
VOffset = VOffsetDef->getOperand(1).getReg();